\doxysection{C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/\+Legacy/stm32\+\_\+hal\+\_\+legacy.h File Reference}
\hypertarget{stm32__hal__legacy_8h}{}\label{stm32__hal__legacy_8h}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/Legacy/stm32\_hal\_legacy.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/Legacy/stm32\_hal\_legacy.h}}


This file contains aliases definition for the STM32\+Cube HAL constants macros and functions maintained for legacy purpose.  


\doxysubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define {\bfseries AES\+\_\+\+FLAG\+\_\+\+RDERR}~CRYP\+\_\+\+FLAG\+\_\+\+RDERR
\item 
\#define {\bfseries AES\+\_\+\+FLAG\+\_\+\+WRERR}~CRYP\+\_\+\+FLAG\+\_\+\+WRERR
\item 
\#define {\bfseries AES\+\_\+\+CLEARFLAG\+\_\+\+CCF}~CRYP\+\_\+\+CLEARFLAG\+\_\+\+CCF
\item 
\#define {\bfseries AES\+\_\+\+CLEARFLAG\+\_\+\+RDERR}~CRYP\+\_\+\+CLEARFLAG\+\_\+\+RDERR
\item 
\#define {\bfseries AES\+\_\+\+CLEARFLAG\+\_\+\+WRERR}~CRYP\+\_\+\+CLEARFLAG\+\_\+\+WRERR
\item 
\#define {\bfseries ADC\+\_\+\+RESOLUTION12b}~ADC\+\_\+\+RESOLUTION\+\_\+12B
\item 
\#define {\bfseries ADC\+\_\+\+RESOLUTION10b}~ADC\+\_\+\+RESOLUTION\+\_\+10B
\item 
\#define {\bfseries ADC\+\_\+\+RESOLUTION8b}~ADC\+\_\+\+RESOLUTION\+\_\+8B
\item 
\#define {\bfseries ADC\+\_\+\+RESOLUTION6b}~ADC\+\_\+\+RESOLUTION\+\_\+6B
\item 
\#define {\bfseries OVR\+\_\+\+DATA\+\_\+\+OVERWRITTEN}~ADC\+\_\+\+OVR\+\_\+\+DATA\+\_\+\+OVERWRITTEN
\item 
\#define {\bfseries OVR\+\_\+\+DATA\+\_\+\+PRESERVED}~ADC\+\_\+\+OVR\+\_\+\+DATA\+\_\+\+PRESERVED
\item 
\#define {\bfseries EOC\+\_\+\+SINGLE\+\_\+\+CONV}~ADC\+\_\+\+EOC\+\_\+\+SINGLE\+\_\+\+CONV
\item 
\#define {\bfseries EOC\+\_\+\+SEQ\+\_\+\+CONV}~ADC\+\_\+\+EOC\+\_\+\+SEQ\+\_\+\+CONV
\item 
\#define {\bfseries EOC\+\_\+\+SINGLE\+\_\+\+SEQ\+\_\+\+CONV}~ADC\+\_\+\+EOC\+\_\+\+SINGLE\+\_\+\+SEQ\+\_\+\+CONV
\item 
\#define {\bfseries REGULAR\+\_\+\+GROUP}~ADC\+\_\+\+REGULAR\+\_\+\+GROUP
\item 
\#define {\bfseries INJECTED\+\_\+\+GROUP}~ADC\+\_\+\+INJECTED\+\_\+\+GROUP
\item 
\#define {\bfseries REGULAR\+\_\+\+INJECTED\+\_\+\+GROUP}~ADC\+\_\+\+REGULAR\+\_\+\+INJECTED\+\_\+\+GROUP
\item 
\#define {\bfseries AWD\+\_\+\+EVENT}~ADC\+\_\+\+AWD\+\_\+\+EVENT
\item 
\#define {\bfseries AWD1\+\_\+\+EVENT}~ADC\+\_\+\+AWD1\+\_\+\+EVENT
\item 
\#define {\bfseries AWD2\+\_\+\+EVENT}~ADC\+\_\+\+AWD2\+\_\+\+EVENT
\item 
\#define {\bfseries AWD3\+\_\+\+EVENT}~ADC\+\_\+\+AWD3\+\_\+\+EVENT
\item 
\#define {\bfseries OVR\+\_\+\+EVENT}~ADC\+\_\+\+OVR\+\_\+\+EVENT
\item 
\#define {\bfseries JQOVF\+\_\+\+EVENT}~ADC\+\_\+\+JQOVF\+\_\+\+EVENT
\item 
\#define {\bfseries ALL\+\_\+\+CHANNELS}~ADC\+\_\+\+ALL\+\_\+\+CHANNELS
\item 
\#define {\bfseries REGULAR\+\_\+\+CHANNELS}~ADC\+\_\+\+REGULAR\+\_\+\+CHANNELS
\item 
\#define {\bfseries INJECTED\+\_\+\+CHANNELS}~ADC\+\_\+\+INJECTED\+\_\+\+CHANNELS
\item 
\#define {\bfseries SYSCFG\+\_\+\+FLAG\+\_\+\+SENSOR\+\_\+\+ADC}~ADC\+\_\+\+FLAG\+\_\+\+SENSOR
\item 
\#define {\bfseries SYSCFG\+\_\+\+FLAG\+\_\+\+VREF\+\_\+\+ADC}~ADC\+\_\+\+FLAG\+\_\+\+VREFINT
\item 
\#define {\bfseries ADC\+\_\+\+CLOCKPRESCALER\+\_\+\+PCLK\+\_\+\+DIV1}~ADC\+\_\+\+CLOCK\+\_\+\+SYNC\+\_\+\+PCLK\+\_\+\+DIV1
\item 
\#define {\bfseries ADC\+\_\+\+CLOCKPRESCALER\+\_\+\+PCLK\+\_\+\+DIV2}~ADC\+\_\+\+CLOCK\+\_\+\+SYNC\+\_\+\+PCLK\+\_\+\+DIV2
\item 
\#define {\bfseries ADC\+\_\+\+CLOCKPRESCALER\+\_\+\+PCLK\+\_\+\+DIV4}~ADC\+\_\+\+CLOCK\+\_\+\+SYNC\+\_\+\+PCLK\+\_\+\+DIV4
\item 
\#define {\bfseries ADC\+\_\+\+CLOCKPRESCALER\+\_\+\+PCLK\+\_\+\+DIV6}~ADC\+\_\+\+CLOCK\+\_\+\+SYNC\+\_\+\+PCLK\+\_\+\+DIV6
\item 
\#define {\bfseries ADC\+\_\+\+CLOCKPRESCALER\+\_\+\+PCLK\+\_\+\+DIV8}~ADC\+\_\+\+CLOCK\+\_\+\+SYNC\+\_\+\+PCLK\+\_\+\+DIV8
\item 
\#define {\bfseries ADC\+\_\+\+EXTERNALTRIG0\+\_\+\+T6\+\_\+\+TRGO}~ADC\+\_\+\+EXTERNALTRIGCONV\+\_\+\+T6\+\_\+\+TRGO
\item 
\#define {\bfseries ADC\+\_\+\+EXTERNALTRIG1\+\_\+\+T21\+\_\+\+CC2}~ADC\+\_\+\+EXTERNALTRIGCONV\+\_\+\+T21\+\_\+\+CC2
\item 
\#define {\bfseries ADC\+\_\+\+EXTERNALTRIG2\+\_\+\+T2\+\_\+\+TRGO}~ADC\+\_\+\+EXTERNALTRIGCONV\+\_\+\+T2\+\_\+\+TRGO
\item 
\#define {\bfseries ADC\+\_\+\+EXTERNALTRIG3\+\_\+\+T2\+\_\+\+CC4}~ADC\+\_\+\+EXTERNALTRIGCONV\+\_\+\+T2\+\_\+\+CC4
\item 
\#define {\bfseries ADC\+\_\+\+EXTERNALTRIG4\+\_\+\+T22\+\_\+\+TRGO}~ADC\+\_\+\+EXTERNALTRIGCONV\+\_\+\+T22\+\_\+\+TRGO
\item 
\#define {\bfseries ADC\+\_\+\+EXTERNALTRIG7\+\_\+\+EXT\+\_\+\+IT11}~ADC\+\_\+\+EXTERNALTRIGCONV\+\_\+\+EXT\+\_\+\+IT11
\item 
\#define {\bfseries ADC\+\_\+\+CLOCK\+\_\+\+ASYNC}~ADC\+\_\+\+CLOCK\+\_\+\+ASYNC\+\_\+\+DIV1
\item 
\#define {\bfseries ADC\+\_\+\+EXTERNALTRIG\+\_\+\+EDGE\+\_\+\+NONE}~ADC\+\_\+\+EXTERNALTRIGCONVEDGE\+\_\+\+NONE
\item 
\#define {\bfseries ADC\+\_\+\+EXTERNALTRIG\+\_\+\+EDGE\+\_\+\+RISING}~ADC\+\_\+\+EXTERNALTRIGCONVEDGE\+\_\+\+RISING
\item 
\#define {\bfseries ADC\+\_\+\+EXTERNALTRIG\+\_\+\+EDGE\+\_\+\+FALLING}~ADC\+\_\+\+EXTERNALTRIGCONVEDGE\+\_\+\+FALLING
\item 
\#define {\bfseries ADC\+\_\+\+EXTERNALTRIG\+\_\+\+EDGE\+\_\+\+RISINGFALLING}~ADC\+\_\+\+EXTERNALTRIGCONVEDGE\+\_\+\+RISINGFALLING
\item 
\#define {\bfseries ADC\+\_\+\+SAMPLETIME\+\_\+2\+CYCLE\+\_\+5}~ADC\+\_\+\+SAMPLETIME\+\_\+2\+CYCLES\+\_\+5
\item 
\#define {\bfseries HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+BUSY\+\_\+\+REG}~HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+REG\+\_\+\+BUSY
\item 
\#define {\bfseries HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+BUSY\+\_\+\+INJ}~HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+INJ\+\_\+\+BUSY
\item 
\#define {\bfseries HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+EOC\+\_\+\+REG}~HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+REG\+\_\+\+EOC
\item 
\#define {\bfseries HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+EOC\+\_\+\+INJ}~HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+INJ\+\_\+\+EOC
\item 
\#define {\bfseries HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+ERROR}~HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+ERROR\+\_\+\+INTERNAL
\item 
\#define {\bfseries HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+BUSY}~HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+BUSY\+\_\+\+INTERNAL
\item 
\#define {\bfseries HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+AWD}~HAL\+\_\+\+ADC\+\_\+\+STATE\+\_\+\+AWD1
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+CEC\+\_\+\+GET\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+CEC\+\_\+\+GET\+\_\+\+FLAG
\item 
\#define {\bfseries COMP\+\_\+\+WINDOWMODE\+\_\+\+DISABLED}~COMP\+\_\+\+WINDOWMODE\+\_\+\+DISABLE
\item 
\#define {\bfseries COMP\+\_\+\+WINDOWMODE\+\_\+\+ENABLED}~COMP\+\_\+\+WINDOWMODE\+\_\+\+ENABLE
\item 
\#define {\bfseries COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP1\+\_\+\+EVENT}~COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP1
\item 
\#define {\bfseries COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP2\+\_\+\+EVENT}~COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP2
\item 
\#define {\bfseries COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP3\+\_\+\+EVENT}~COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP3
\item 
\#define {\bfseries COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP4\+\_\+\+EVENT}~COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP4
\item 
\#define {\bfseries COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP5\+\_\+\+EVENT}~COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP5
\item 
\#define {\bfseries COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP6\+\_\+\+EVENT}~COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP6
\item 
\#define {\bfseries COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP7\+\_\+\+EVENT}~COMP\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+COMP7
\item 
\#define {\bfseries COMP\+\_\+\+OUTPUT\+\_\+\+COMP6\+TIM2\+OCREFCLR}~COMP\+\_\+\+OUTPUT\+\_\+\+COMP6\+\_\+\+TIM2\+OCREFCLR
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+CORTEX\+\_\+\+SYSTICKCLK\+\_\+\+CONFIG}~HAL\+\_\+\+SYSTICK\+\_\+\+CLKSource\+Config
\item 
\#define \mbox{\hyperlink{group___c_r_c___aliases_ga1740ace1886a861bdd009f9b841a6d88}{HAL\+\_\+\+CRC\+\_\+\+Input\+\_\+\+Data\+\_\+\+Reverse}}~HAL\+\_\+\+CRCEx\+\_\+\+Input\+\_\+\+Data\+\_\+\+Reverse
\item 
\#define \mbox{\hyperlink{group___c_r_c___aliases_ga27037619e08342b7855dd25d384c1b37}{HAL\+\_\+\+CRC\+\_\+\+Output\+\_\+\+Data\+\_\+\+Reverse}}~HAL\+\_\+\+CRCEx\+\_\+\+Output\+\_\+\+Data\+\_\+\+Reverse
\item 
\#define {\bfseries CRC\+\_\+\+OUTPUTDATA\+\_\+\+INVERSION\+\_\+\+DISABLED}~CRC\+\_\+\+OUTPUTDATA\+\_\+\+INVERSION\+\_\+\+DISABLE
\item 
\#define {\bfseries CRC\+\_\+\+OUTPUTDATA\+\_\+\+INVERSION\+\_\+\+ENABLED}~CRC\+\_\+\+OUTPUTDATA\+\_\+\+INVERSION\+\_\+\+ENABLE
\item 
\#define {\bfseries DAC1\+\_\+\+CHANNEL\+\_\+1}~DAC\+\_\+\+CHANNEL\+\_\+1
\item 
\#define {\bfseries DAC1\+\_\+\+CHANNEL\+\_\+2}~DAC\+\_\+\+CHANNEL\+\_\+2
\item 
\#define {\bfseries DAC2\+\_\+\+CHANNEL\+\_\+1}~DAC\+\_\+\+CHANNEL\+\_\+1
\item 
\#define {\bfseries DAC\+\_\+\+WAVE\+\_\+\+NONE}~0x00000000U
\item 
\#define {\bfseries DAC\+\_\+\+WAVE\+\_\+\+NOISE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0871e6466e3a7378103c431832ae525a}{DAC\+\_\+\+CR\+\_\+\+WAVE1\+\_\+0}}
\item 
\#define {\bfseries DAC\+\_\+\+WAVE\+\_\+\+TRIANGLE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga48e167ae02d2ad5bc9fd30c2f8ea5b37}{DAC\+\_\+\+CR\+\_\+\+WAVE1\+\_\+1}}
\item 
\#define {\bfseries DAC\+\_\+\+WAVEGENERATION\+\_\+\+NONE}~DAC\+\_\+\+WAVE\+\_\+\+NONE
\item 
\#define {\bfseries DAC\+\_\+\+WAVEGENERATION\+\_\+\+NOISE}~DAC\+\_\+\+WAVE\+\_\+\+NOISE
\item 
\#define {\bfseries DAC\+\_\+\+WAVEGENERATION\+\_\+\+TRIANGLE}~DAC\+\_\+\+WAVE\+\_\+\+TRIANGLE
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+ADC\+\_\+\+DMA\+\_\+\+CH2}~DMA\+\_\+\+REMAP\+\_\+\+ADC\+\_\+\+DMA\+\_\+\+CH2
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+USART1\+\_\+\+TX\+\_\+\+DMA\+\_\+\+CH4}~DMA\+\_\+\+REMAP\+\_\+\+USART1\+\_\+\+TX\+\_\+\+DMA\+\_\+\+CH4
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+USART1\+\_\+\+RX\+\_\+\+DMA\+\_\+\+CH5}~DMA\+\_\+\+REMAP\+\_\+\+USART1\+\_\+\+RX\+\_\+\+DMA\+\_\+\+CH5
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+TIM16\+\_\+\+DMA\+\_\+\+CH4}~DMA\+\_\+\+REMAP\+\_\+\+TIM16\+\_\+\+DMA\+\_\+\+CH4
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+TIM17\+\_\+\+DMA\+\_\+\+CH2}~DMA\+\_\+\+REMAP\+\_\+\+TIM17\+\_\+\+DMA\+\_\+\+CH2
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+USART3\+\_\+\+DMA\+\_\+\+CH32}~DMA\+\_\+\+REMAP\+\_\+\+USART3\+\_\+\+DMA\+\_\+\+CH32
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+TIM16\+\_\+\+DMA\+\_\+\+CH6}~DMA\+\_\+\+REMAP\+\_\+\+TIM16\+\_\+\+DMA\+\_\+\+CH6
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+TIM17\+\_\+\+DMA\+\_\+\+CH7}~DMA\+\_\+\+REMAP\+\_\+\+TIM17\+\_\+\+DMA\+\_\+\+CH7
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+SPI2\+\_\+\+DMA\+\_\+\+CH67}~DMA\+\_\+\+REMAP\+\_\+\+SPI2\+\_\+\+DMA\+\_\+\+CH67
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+USART2\+\_\+\+DMA\+\_\+\+CH67}~DMA\+\_\+\+REMAP\+\_\+\+USART2\+\_\+\+DMA\+\_\+\+CH67
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+I2\+C1\+\_\+\+DMA\+\_\+\+CH76}~DMA\+\_\+\+REMAP\+\_\+\+I2\+C1\+\_\+\+DMA\+\_\+\+CH76
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+TIM1\+\_\+\+DMA\+\_\+\+CH6}~DMA\+\_\+\+REMAP\+\_\+\+TIM1\+\_\+\+DMA\+\_\+\+CH6
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+TIM2\+\_\+\+DMA\+\_\+\+CH7}~DMA\+\_\+\+REMAP\+\_\+\+TIM2\+\_\+\+DMA\+\_\+\+CH7
\item 
\#define {\bfseries HAL\+\_\+\+REMAPDMA\+\_\+\+TIM3\+\_\+\+DMA\+\_\+\+CH6}~DMA\+\_\+\+REMAP\+\_\+\+TIM3\+\_\+\+DMA\+\_\+\+CH6
\item 
\#define {\bfseries IS\+\_\+\+HAL\+\_\+\+REMAPDMA}~IS\+\_\+\+DMA\+\_\+\+REMAP
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+REMAPDMA\+\_\+\+CHANNEL\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+DMA\+\_\+\+REMAP\+\_\+\+CHANNEL\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+REMAPDMA\+\_\+\+CHANNEL\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+DMA\+\_\+\+REMAP\+\_\+\+CHANNEL\+\_\+\+DISABLE
\item 
\#define {\bfseries TYPEPROGRAM\+\_\+\+BYTE}~FLASH\+\_\+\+TYPEPROGRAM\+\_\+\+BYTE
\item 
\#define {\bfseries TYPEPROGRAM\+\_\+\+HALFWORD}~FLASH\+\_\+\+TYPEPROGRAM\+\_\+\+HALFWORD
\item 
\#define {\bfseries TYPEPROGRAM\+\_\+\+WORD}~FLASH\+\_\+\+TYPEPROGRAM\+\_\+\+WORD
\item 
\#define {\bfseries TYPEPROGRAM\+\_\+\+DOUBLEWORD}~FLASH\+\_\+\+TYPEPROGRAM\+\_\+\+DOUBLEWORD
\item 
\#define {\bfseries TYPEERASE\+\_\+\+SECTORS}~\mbox{\hyperlink{group___f_l_a_s_h_ex___type___erase_gaee700cbbc746cf72fca3ebf07ee20c4e}{FLASH\+\_\+\+TYPEERASE\+\_\+\+SECTORS}}
\item 
\#define {\bfseries TYPEERASE\+\_\+\+PAGES}~FLASH\+\_\+\+TYPEERASE\+\_\+\+PAGES
\item 
\#define {\bfseries TYPEERASE\+\_\+\+PAGEERASE}~FLASH\+\_\+\+TYPEERASE\+\_\+\+PAGES
\item 
\#define {\bfseries TYPEERASE\+\_\+\+MASSERASE}~\mbox{\hyperlink{group___f_l_a_s_h_ex___type___erase_ga9bc03534e69c625e1b4f0f05c3852243}{FLASH\+\_\+\+TYPEERASE\+\_\+\+MASSERASE}}
\item 
\#define {\bfseries WRPSTATE\+\_\+\+DISABLE}~\mbox{\hyperlink{group___f_l_a_s_h_ex___w_r_p___state_gaa34eb6205fe554f65a311ee974d5a4ab}{OB\+\_\+\+WRPSTATE\+\_\+\+DISABLE}}
\item 
\#define {\bfseries WRPSTATE\+\_\+\+ENABLE}~\mbox{\hyperlink{group___f_l_a_s_h_ex___w_r_p___state_ga9fc463145ab57616baa36d95523186a1}{OB\+\_\+\+WRPSTATE\+\_\+\+ENABLE}}
\item 
\#define {\bfseries HAL\+\_\+\+FLASH\+\_\+\+TIMEOUT\+\_\+\+VALUE}~FLASH\+\_\+\+TIMEOUT\+\_\+\+VALUE
\item 
\#define {\bfseries OBEX\+\_\+\+PCROP}~\mbox{\hyperlink{group___f_l_a_s_h_ex___option___type_gade16326e09bd923b54f1ec8622a7bc4b}{OPTIONBYTE\+\_\+\+PCROP}}
\item 
\#define {\bfseries OBEX\+\_\+\+BOOTCONFIG}~OPTIONBYTE\+\_\+\+BOOTCONFIG
\item 
\#define {\bfseries PCROPSTATE\+\_\+\+DISABLE}~OB\+\_\+\+PCROP\+\_\+\+STATE\+\_\+\+DISABLE
\item 
\#define {\bfseries PCROPSTATE\+\_\+\+ENABLE}~OB\+\_\+\+PCROP\+\_\+\+STATE\+\_\+\+ENABLE
\item 
\#define {\bfseries TYPEERASEDATA\+\_\+\+BYTE}~FLASH\+\_\+\+TYPEERASEDATA\+\_\+\+BYTE
\item 
\#define {\bfseries TYPEERASEDATA\+\_\+\+HALFWORD}~FLASH\+\_\+\+TYPEERASEDATA\+\_\+\+HALFWORD
\item 
\#define {\bfseries TYPEERASEDATA\+\_\+\+WORD}~FLASH\+\_\+\+TYPEERASEDATA\+\_\+\+WORD
\item 
\#define {\bfseries TYPEPROGRAMDATA\+\_\+\+BYTE}~FLASH\+\_\+\+TYPEPROGRAMDATA\+\_\+\+BYTE
\item 
\#define {\bfseries TYPEPROGRAMDATA\+\_\+\+HALFWORD}~FLASH\+\_\+\+TYPEPROGRAMDATA\+\_\+\+HALFWORD
\item 
\#define {\bfseries TYPEPROGRAMDATA\+\_\+\+WORD}~FLASH\+\_\+\+TYPEPROGRAMDATA\+\_\+\+WORD
\item 
\#define {\bfseries TYPEPROGRAMDATA\+\_\+\+FASTBYTE}~FLASH\+\_\+\+TYPEPROGRAMDATA\+\_\+\+FASTBYTE
\item 
\#define {\bfseries TYPEPROGRAMDATA\+\_\+\+FASTHALFWORD}~FLASH\+\_\+\+TYPEPROGRAMDATA\+\_\+\+FASTHALFWORD
\item 
\#define {\bfseries TYPEPROGRAMDATA\+\_\+\+FASTWORD}~FLASH\+\_\+\+TYPEPROGRAMDATA\+\_\+\+FASTWORD
\item 
\#define {\bfseries PAGESIZE}~FLASH\+\_\+\+PAGE\+\_\+\+SIZE
\item 
\#define {\bfseries TYPEPROGRAM\+\_\+\+FASTBYTE}~FLASH\+\_\+\+TYPEPROGRAM\+\_\+\+BYTE
\item 
\#define {\bfseries TYPEPROGRAM\+\_\+\+FASTHALFWORD}~FLASH\+\_\+\+TYPEPROGRAM\+\_\+\+HALFWORD
\item 
\#define {\bfseries TYPEPROGRAM\+\_\+\+FASTWORD}~FLASH\+\_\+\+TYPEPROGRAM\+\_\+\+WORD
\item 
\#define {\bfseries VOLTAGE\+\_\+\+RANGE\+\_\+1}~FLASH\+\_\+\+VOLTAGE\+\_\+\+RANGE\+\_\+1
\item 
\#define {\bfseries VOLTAGE\+\_\+\+RANGE\+\_\+2}~FLASH\+\_\+\+VOLTAGE\+\_\+\+RANGE\+\_\+2
\item 
\#define {\bfseries VOLTAGE\+\_\+\+RANGE\+\_\+3}~FLASH\+\_\+\+VOLTAGE\+\_\+\+RANGE\+\_\+3
\item 
\#define {\bfseries VOLTAGE\+\_\+\+RANGE\+\_\+4}~FLASH\+\_\+\+VOLTAGE\+\_\+\+RANGE\+\_\+4
\item 
\#define {\bfseries TYPEPROGRAM\+\_\+\+FAST}~FLASH\+\_\+\+TYPEPROGRAM\+\_\+\+FAST
\item 
\#define {\bfseries TYPEPROGRAM\+\_\+\+FAST\+\_\+\+AND\+\_\+\+LAST}~FLASH\+\_\+\+TYPEPROGRAM\+\_\+\+FAST\+\_\+\+AND\+\_\+\+LAST
\item 
\#define {\bfseries WRPAREA\+\_\+\+BANK1\+\_\+\+AREAA}~OB\+\_\+\+WRPAREA\+\_\+\+BANK1\+\_\+\+AREAA
\item 
\#define {\bfseries WRPAREA\+\_\+\+BANK1\+\_\+\+AREAB}~OB\+\_\+\+WRPAREA\+\_\+\+BANK1\+\_\+\+AREAB
\item 
\#define {\bfseries WRPAREA\+\_\+\+BANK2\+\_\+\+AREAA}~OB\+\_\+\+WRPAREA\+\_\+\+BANK2\+\_\+\+AREAA
\item 
\#define {\bfseries WRPAREA\+\_\+\+BANK2\+\_\+\+AREAB}~OB\+\_\+\+WRPAREA\+\_\+\+BANK2\+\_\+\+AREAB
\item 
\#define {\bfseries IWDG\+\_\+\+STDBY\+\_\+\+FREEZE}~\mbox{\hyperlink{group___f_l_a_s_h_ex___option___bytes___i_w_d_g___f_r_e_e_z_e___s_a_n_d_b_y_ga2033b993c192a55757fc3fb0d8cfebc9}{OB\+\_\+\+IWDG\+\_\+\+STDBY\+\_\+\+FREEZE}}
\item 
\#define {\bfseries IWDG\+\_\+\+STDBY\+\_\+\+ACTIVE}~OB\+\_\+\+IWDG\+\_\+\+STDBY\+\_\+\+RUN
\item 
\#define {\bfseries IWDG\+\_\+\+STOP\+\_\+\+FREEZE}~\mbox{\hyperlink{group___f_l_a_s_h_ex___option___bytes___i_w_d_g___f_r_e_e_z_e___s_t_o_p_gae0c882a6f14ebe5d1969b50d5a2dbb17}{OB\+\_\+\+IWDG\+\_\+\+STOP\+\_\+\+FREEZE}}
\item 
\#define {\bfseries IWDG\+\_\+\+STOP\+\_\+\+ACTIVE}~OB\+\_\+\+IWDG\+\_\+\+STOP\+\_\+\+RUN
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+NONE}~\mbox{\hyperlink{group___f_l_a_s_h___error___code_gae7fb9ee7198d393aba27ade3a9f50a70}{HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+NONE}}
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+RD}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+RD
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+PG}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+PROG
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+PGP}~\mbox{\hyperlink{group___f_l_a_s_h___error___code_ga7132ff3b7f45c0cfe818d61bdb01dc64}{HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+PGS}}
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+WRP}~\mbox{\hyperlink{group___f_l_a_s_h___error___code_ga27e871d85f9311272098315bc3723075}{HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+WRP}}
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+OPTV}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+OPTV
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+OPTVUSR}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+OPTVUSR
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+PROG}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+PROG
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+OP}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+OPERATION
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+PGA}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+PGA
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+SIZE}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+SIZE
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+SIZ}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+SIZE
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+PGS}~\mbox{\hyperlink{group___f_l_a_s_h___error___code_ga7132ff3b7f45c0cfe818d61bdb01dc64}{HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+PGS}}
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+MIS}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+MIS
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+FAST}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+FAST
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+FWWERR}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+FWWERR
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+NOTZERO}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+NOTZERO
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+OPERATION}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+OPERATION
\item 
\#define {\bfseries FLASH\+\_\+\+ERROR\+\_\+\+ERS}~HAL\+\_\+\+FLASH\+\_\+\+ERROR\+\_\+\+ERS
\item 
\#define {\bfseries OB\+\_\+\+WDG\+\_\+\+SW}~\mbox{\hyperlink{group___f_l_a_s_h_ex___option___bytes___i_watchdog_ga5a357e232c955444c3f2ccb9a937ffce}{OB\+\_\+\+IWDG\+\_\+\+SW}}
\item 
\#define {\bfseries OB\+\_\+\+WDG\+\_\+\+HW}~\mbox{\hyperlink{group___f_l_a_s_h_ex___option___bytes___i_watchdog_gadfcbfa963d79c339ec8e2d5a7734e47a}{OB\+\_\+\+IWDG\+\_\+\+HW}}
\item 
\#define {\bfseries OB\+\_\+\+SDADC12\+\_\+\+VDD\+\_\+\+MONITOR\+\_\+\+SET}~OB\+\_\+\+SDACD\+\_\+\+VDD\+\_\+\+MONITOR\+\_\+\+SET
\item 
\#define {\bfseries OB\+\_\+\+SDADC12\+\_\+\+VDD\+\_\+\+MONITOR\+\_\+\+RESET}~OB\+\_\+\+SDACD\+\_\+\+VDD\+\_\+\+MONITOR\+\_\+\+RESET
\item 
\#define {\bfseries OB\+\_\+\+RAM\+\_\+\+PARITY\+\_\+\+CHECK\+\_\+\+SET}~OB\+\_\+\+SRAM\+\_\+\+PARITY\+\_\+\+SET
\item 
\#define {\bfseries OB\+\_\+\+RAM\+\_\+\+PARITY\+\_\+\+CHECK\+\_\+\+RESET}~OB\+\_\+\+SRAM\+\_\+\+PARITY\+\_\+\+RESET
\item 
\#define {\bfseries IS\+\_\+\+OB\+\_\+\+SDADC12\+\_\+\+VDD\+\_\+\+MONITOR}~IS\+\_\+\+OB\+\_\+\+SDACD\+\_\+\+VDD\+\_\+\+MONITOR
\item 
\#define {\bfseries OB\+\_\+\+RDP\+\_\+\+LEVEL0}~OB\+\_\+\+RDP\+\_\+\+LEVEL\+\_\+0
\item 
\#define {\bfseries OB\+\_\+\+RDP\+\_\+\+LEVEL1}~OB\+\_\+\+RDP\+\_\+\+LEVEL\+\_\+1
\item 
\#define {\bfseries OB\+\_\+\+RDP\+\_\+\+LEVEL2}~\mbox{\hyperlink{group___f_l_a_s_h_ex___option___bytes___read___protection_ga2262afca565429ce2808d835c49e5ee6}{OB\+\_\+\+RDP\+\_\+\+LEVEL\+\_\+2}}
\item 
\#define {\bfseries OB\+\_\+\+BOOT\+\_\+\+ENTRY\+\_\+\+FORCED\+\_\+\+NONE}~OB\+\_\+\+BOOT\+\_\+\+LOCK\+\_\+\+DISABLE
\item 
\#define {\bfseries OB\+\_\+\+BOOT\+\_\+\+ENTRY\+\_\+\+FORCED\+\_\+\+FLASH}~OB\+\_\+\+BOOT\+\_\+\+LOCK\+\_\+\+ENABLE
\item 
\#define {\bfseries HAL\+\_\+\+SYSCFG\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C\+\_\+\+PA9}~I2\+C\+\_\+\+FASTMODEPLUS\+\_\+\+PA9
\item 
\#define {\bfseries HAL\+\_\+\+SYSCFG\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C\+\_\+\+PA10}~I2\+C\+\_\+\+FASTMODEPLUS\+\_\+\+PA10
\item 
\#define {\bfseries HAL\+\_\+\+SYSCFG\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C\+\_\+\+PB6}~\mbox{\hyperlink{group___i2_c_ex___fast_mode_plus_ga9b3b77b0f00f09ee6d272d70dd5663f5}{I2\+C\+\_\+\+FASTMODEPLUS\+\_\+\+PB6}}
\item 
\#define {\bfseries HAL\+\_\+\+SYSCFG\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C\+\_\+\+PB7}~\mbox{\hyperlink{group___i2_c_ex___fast_mode_plus_gaaa6d3f6c1d635a2f5e4dbe2ef66ce1c3}{I2\+C\+\_\+\+FASTMODEPLUS\+\_\+\+PB7}}
\item 
\#define {\bfseries HAL\+\_\+\+SYSCFG\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C\+\_\+\+PB8}~\mbox{\hyperlink{group___i2_c_ex___fast_mode_plus_gaf8d6aa219f041b552b3d3cd53cb78a26}{I2\+C\+\_\+\+FASTMODEPLUS\+\_\+\+PB8}}
\item 
\#define {\bfseries HAL\+\_\+\+SYSCFG\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C\+\_\+\+PB9}~\mbox{\hyperlink{group___i2_c_ex___fast_mode_plus_gafab6e63d100bf337bf9f0bf6a607636d}{I2\+C\+\_\+\+FASTMODEPLUS\+\_\+\+PB9}}
\item 
\#define {\bfseries HAL\+\_\+\+SYSCFG\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C1}~\mbox{\hyperlink{group___i2_c_ex___fast_mode_plus_ga3a8064ecfa3b33115f62123f7162770e}{I2\+C\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C1}}
\item 
\#define {\bfseries HAL\+\_\+\+SYSCFG\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C2}~\mbox{\hyperlink{group___i2_c_ex___fast_mode_plus_gaa5c33513afa036a6f97e9cbf2d61f4b2}{I2\+C\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C2}}
\item 
\#define {\bfseries HAL\+\_\+\+SYSCFG\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C3}~\mbox{\hyperlink{group___i2_c_ex___fast_mode_plus_gafeb5c46154f31ecf6ff77d4ab1d2ee7b}{I2\+C\+\_\+\+FASTMODEPLUS\+\_\+\+I2\+C3}}
\item 
\#define {\bfseries FSMC\+\_\+\+NORSRAM\+\_\+\+TYPEDEF}~FSMC\+\_\+\+NORSRAM\+\_\+\+Type\+Def
\item 
\#define {\bfseries FSMC\+\_\+\+NORSRAM\+\_\+\+EXTENDED\+\_\+\+TYPEDEF}~FSMC\+\_\+\+NORSRAM\+\_\+\+EXTENDED\+\_\+\+Type\+Def
\item 
\#define {\bfseries GET\+\_\+\+GPIO\+\_\+\+SOURCE}~GPIO\+\_\+\+GET\+\_\+\+INDEX
\item 
\#define {\bfseries GET\+\_\+\+GPIO\+\_\+\+INDEX}~GPIO\+\_\+\+GET\+\_\+\+INDEX
\item 
\#define {\bfseries GPIO\+\_\+\+AF0\+\_\+\+LPTIM}~GPIO\+\_\+\+AF0\+\_\+\+LPTIM1
\item 
\#define {\bfseries GPIO\+\_\+\+AF1\+\_\+\+LPTIM}~GPIO\+\_\+\+AF1\+\_\+\+LPTIM1
\item 
\#define {\bfseries GPIO\+\_\+\+AF2\+\_\+\+LPTIM}~GPIO\+\_\+\+AF2\+\_\+\+LPTIM1
\item 
\#define {\bfseries GPIO\+\_\+\+AF6\+\_\+\+DFSDM}~GPIO\+\_\+\+AF6\+\_\+\+DFSDM1
\item 
\#define {\bfseries HRTIM\+\_\+\+TIMDELAYEDPROTECTION\+\_\+\+DISABLED}~HRTIM\+\_\+\+TIMER\+\_\+\+A\+\_\+\+B\+\_\+\+C\+\_\+\+DELAYEDPROTECTION\+\_\+\+DISABLED
\item 
\#define {\bfseries HRTIM\+\_\+\+TIMDELAYEDPROTECTION\+\_\+\+DELAYEDOUT1\+\_\+\+EEV68}~HRTIM\+\_\+\+TIMER\+\_\+\+A\+\_\+\+B\+\_\+\+C\+\_\+\+DELAYEDPROTECTION\+\_\+\+DELAYEDOUT1\+\_\+\+EEV6
\item 
\#define {\bfseries HRTIM\+\_\+\+TIMDELAYEDPROTECTION\+\_\+\+DELAYEDOUT2\+\_\+\+EEV68}~HRTIM\+\_\+\+TIMER\+\_\+\+A\+\_\+\+B\+\_\+\+C\+\_\+\+DELAYEDPROTECTION\+\_\+\+DELAYEDOUT2\+\_\+\+EEV6
\item 
\#define {\bfseries HRTIM\+\_\+\+TIMDELAYEDPROTECTION\+\_\+\+DELAYEDBOTH\+\_\+\+EEV68}~HRTIM\+\_\+\+TIMER\+\_\+\+A\+\_\+\+B\+\_\+\+C\+\_\+\+DELAYEDPROTECTION\+\_\+\+DELAYEDBOTH\+\_\+\+EEV6
\item 
\#define {\bfseries HRTIM\+\_\+\+TIMDELAYEDPROTECTION\+\_\+\+BALANCED\+\_\+\+EEV68}~HRTIM\+\_\+\+TIMER\+\_\+\+A\+\_\+\+B\+\_\+\+C\+\_\+\+DELAYEDPROTECTION\+\_\+\+BALANCED\+\_\+\+EEV6
\item 
\#define {\bfseries HRTIM\+\_\+\+TIMDELAYEDPROTECTION\+\_\+\+DELAYEDOUT1\+\_\+\+DEEV79}~HRTIM\+\_\+\+TIMER\+\_\+\+A\+\_\+\+B\+\_\+\+C\+\_\+\+DELAYEDPROTECTION\+\_\+\+DELAYEDOUT1\+\_\+\+DEEV7
\item 
\#define {\bfseries HRTIM\+\_\+\+TIMDELAYEDPROTECTION\+\_\+\+DELAYEDOUT2\+\_\+\+DEEV79}~HRTIM\+\_\+\+TIMER\+\_\+\+A\+\_\+\+B\+\_\+\+C\+\_\+\+DELAYEDPROTECTION\+\_\+\+DELAYEDOUT2\+\_\+\+DEEV7
\item 
\#define {\bfseries HRTIM\+\_\+\+TIMDELAYEDPROTECTION\+\_\+\+DELAYEDBOTH\+\_\+\+EEV79}~HRTIM\+\_\+\+TIMER\+\_\+\+A\+\_\+\+B\+\_\+\+C\+\_\+\+DELAYEDPROTECTION\+\_\+\+DELAYEDBOTH\+\_\+\+EEV7
\item 
\#define {\bfseries HRTIM\+\_\+\+TIMDELAYEDPROTECTION\+\_\+\+BALANCED\+\_\+\+EEV79}~HRTIM\+\_\+\+TIMER\+\_\+\+A\+\_\+\+B\+\_\+\+C\+\_\+\+DELAYEDPROTECTION\+\_\+\+BALANCED\+\_\+\+EEV7
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+Set\+Counter}~\+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+SETCOUNTER
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+Get\+Counter}~\+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+GETCOUNTER
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+Set\+Period}~\+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+SETPERIOD
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+Get\+Period}~\+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+GETPERIOD
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+Set\+Clock\+Prescaler}~\+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+SETCLOCKPRESCALER
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+Get\+Clock\+Prescaler}~\+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+GETCLOCKPRESCALER
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+Set\+Compare}~\+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+SETCOMPARE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+Get\+Compare}~\+\_\+\+\_\+\+HAL\+\_\+\+HRTIM\+\_\+\+GETCOMPARE
\item 
\#define {\bfseries I2\+C\+\_\+\+DUALADDRESS\+\_\+\+DISABLED}~I2\+C\+\_\+\+DUALADDRESS\+\_\+\+DISABLE
\item 
\#define {\bfseries I2\+C\+\_\+\+DUALADDRESS\+\_\+\+ENABLED}~I2\+C\+\_\+\+DUALADDRESS\+\_\+\+ENABLE
\item 
\#define {\bfseries I2\+C\+\_\+\+GENERALCALL\+\_\+\+DISABLED}~I2\+C\+\_\+\+GENERALCALL\+\_\+\+DISABLE
\item 
\#define {\bfseries I2\+C\+\_\+\+GENERALCALL\+\_\+\+ENABLED}~I2\+C\+\_\+\+GENERALCALL\+\_\+\+ENABLE
\item 
\#define {\bfseries I2\+C\+\_\+\+NOSTRETCH\+\_\+\+DISABLED}~I2\+C\+\_\+\+NOSTRETCH\+\_\+\+DISABLE
\item 
\#define {\bfseries I2\+C\+\_\+\+NOSTRETCH\+\_\+\+ENABLED}~I2\+C\+\_\+\+NOSTRETCH\+\_\+\+ENABLE
\item 
\#define {\bfseries I2\+C\+\_\+\+ANALOGFILTER\+\_\+\+ENABLED}~I2\+C\+\_\+\+ANALOGFILTER\+\_\+\+ENABLE
\item 
\#define {\bfseries I2\+C\+\_\+\+ANALOGFILTER\+\_\+\+DISABLED}~I2\+C\+\_\+\+ANALOGFILTER\+\_\+\+DISABLE
\item 
\#define {\bfseries IRDA\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+DISABLED}~IRDA\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+DISABLE
\item 
\#define {\bfseries IRDA\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+ENABLED}~IRDA\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+ENABLE
\item 
\#define {\bfseries KR\+\_\+\+KEY\+\_\+\+RELOAD}~IWDG\+\_\+\+KEY\+\_\+\+RELOAD
\item 
\#define {\bfseries KR\+\_\+\+KEY\+\_\+\+ENABLE}~IWDG\+\_\+\+KEY\+\_\+\+ENABLE
\item 
\#define {\bfseries KR\+\_\+\+KEY\+\_\+\+EWA}~IWDG\+\_\+\+KEY\+\_\+\+WRITE\+\_\+\+ACCESS\+\_\+\+ENABLE
\item 
\#define {\bfseries KR\+\_\+\+KEY\+\_\+\+DWA}~IWDG\+\_\+\+KEY\+\_\+\+WRITE\+\_\+\+ACCESS\+\_\+\+DISABLE
\item 
\#define {\bfseries LPTIM\+\_\+\+CLOCKSAMPLETIME\+\_\+\+DIRECTTRANSISTION}~LPTIM\+\_\+\+CLOCKSAMPLETIME\+\_\+\+DIRECTTRANSITION
\item 
\#define {\bfseries LPTIM\+\_\+\+CLOCKSAMPLETIME\+\_\+2\+TRANSISTIONS}~LPTIM\+\_\+\+CLOCKSAMPLETIME\+\_\+2\+TRANSITIONS
\item 
\#define {\bfseries LPTIM\+\_\+\+CLOCKSAMPLETIME\+\_\+4\+TRANSISTIONS}~LPTIM\+\_\+\+CLOCKSAMPLETIME\+\_\+4\+TRANSITIONS
\item 
\#define {\bfseries LPTIM\+\_\+\+CLOCKSAMPLETIME\+\_\+8\+TRANSISTIONS}~LPTIM\+\_\+\+CLOCKSAMPLETIME\+\_\+8\+TRANSITIONS
\item 
\#define {\bfseries LPTIM\+\_\+\+CLOCKPOLARITY\+\_\+\+RISINGEDGE}~LPTIM\+\_\+\+CLOCKPOLARITY\+\_\+\+RISING
\item 
\#define {\bfseries LPTIM\+\_\+\+CLOCKPOLARITY\+\_\+\+FALLINGEDGE}~LPTIM\+\_\+\+CLOCKPOLARITY\+\_\+\+FALLING
\item 
\#define {\bfseries LPTIM\+\_\+\+CLOCKPOLARITY\+\_\+\+BOTHEDGES}~LPTIM\+\_\+\+CLOCKPOLARITY\+\_\+\+RISING\+\_\+\+FALLING
\item 
\#define {\bfseries LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+\+DIRECTTRANSISTION}~LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+\+DIRECTTRANSITION
\item 
\#define {\bfseries LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+2\+TRANSISTIONS}~LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+2\+TRANSITIONS
\item 
\#define {\bfseries LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+4\+TRANSISTIONS}~LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+4\+TRANSITIONS
\item 
\#define {\bfseries LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+8\+TRANSISTIONS}~LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+8\+TRANSITIONS
\item 
\#define {\bfseries LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+2\+TRANSITION}~LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+2\+TRANSITIONS
\item 
\#define {\bfseries LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+4\+TRANSITION}~LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+4\+TRANSITIONS
\item 
\#define {\bfseries LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+8\+TRANSITION}~LPTIM\+\_\+\+TRIGSAMPLETIME\+\_\+8\+TRANSITIONS
\item 
\#define {\bfseries HAL\+\_\+\+LPTIM\+\_\+\+Read\+Compare}~HAL\+\_\+\+LPTIM\+\_\+\+Read\+Captured\+Value
\item 
\#define {\bfseries HAL\+\_\+\+NAND\+\_\+\+Read\+\_\+\+Page}~HAL\+\_\+\+NAND\+\_\+\+Read\+\_\+\+Page\+\_\+8b
\item 
\#define {\bfseries HAL\+\_\+\+NAND\+\_\+\+Write\+\_\+\+Page}~HAL\+\_\+\+NAND\+\_\+\+Write\+\_\+\+Page\+\_\+8b
\item 
\#define {\bfseries HAL\+\_\+\+NAND\+\_\+\+Read\+\_\+\+Spare\+Area}~HAL\+\_\+\+NAND\+\_\+\+Read\+\_\+\+Spare\+Area\+\_\+8b
\item 
\#define {\bfseries HAL\+\_\+\+NAND\+\_\+\+Write\+\_\+\+Spare\+Area}~HAL\+\_\+\+NAND\+\_\+\+Write\+\_\+\+Spare\+Area\+\_\+8b
\item 
\#define {\bfseries NAND\+\_\+\+Address\+Typedef}~NAND\+\_\+\+Address\+Type\+Def
\item 
\#define {\bfseries \+\_\+\+\_\+\+ARRAY\+\_\+\+ADDRESS}~ARRAY\+\_\+\+ADDRESS
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADDR\+\_\+1st\+\_\+\+CYCLE}~ADDR\+\_\+1\+ST\+\_\+\+CYCLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADDR\+\_\+2nd\+\_\+\+CYCLE}~ADDR\+\_\+2\+ND\+\_\+\+CYCLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADDR\+\_\+3rd\+\_\+\+CYCLE}~ADDR\+\_\+3\+RD\+\_\+\+CYCLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADDR\+\_\+4th\+\_\+\+CYCLE}~ADDR\+\_\+4\+TH\+\_\+\+CYCLE
\item 
\#define {\bfseries NOR\+\_\+\+Status\+Typedef}~HAL\+\_\+\+NOR\+\_\+\+Status\+Type\+Def
\item 
\#define {\bfseries NOR\+\_\+\+SUCCESS}~HAL\+\_\+\+NOR\+\_\+\+STATUS\+\_\+\+SUCCESS
\item 
\#define {\bfseries NOR\+\_\+\+ONGOING}~HAL\+\_\+\+NOR\+\_\+\+STATUS\+\_\+\+ONGOING
\item 
\#define {\bfseries NOR\+\_\+\+ERROR}~HAL\+\_\+\+NOR\+\_\+\+STATUS\+\_\+\+ERROR
\item 
\#define {\bfseries NOR\+\_\+\+TIMEOUT}~HAL\+\_\+\+NOR\+\_\+\+STATUS\+\_\+\+TIMEOUT
\item 
\#define {\bfseries \+\_\+\+\_\+\+NOR\+\_\+\+WRITE}~NOR\+\_\+\+WRITE
\item 
\#define {\bfseries \+\_\+\+\_\+\+NOR\+\_\+\+ADDR\+\_\+\+SHIFT}~NOR\+\_\+\+ADDR\+\_\+\+SHIFT
\item 
\#define {\bfseries OPAMP\+\_\+\+NONINVERTINGINPUT\+\_\+\+VP0}~OPAMP\+\_\+\+NONINVERTINGINPUT\+\_\+\+IO0
\item 
\#define {\bfseries OPAMP\+\_\+\+NONINVERTINGINPUT\+\_\+\+VP1}~OPAMP\+\_\+\+NONINVERTINGINPUT\+\_\+\+IO1
\item 
\#define {\bfseries OPAMP\+\_\+\+NONINVERTINGINPUT\+\_\+\+VP2}~OPAMP\+\_\+\+NONINVERTINGINPUT\+\_\+\+IO2
\item 
\#define {\bfseries OPAMP\+\_\+\+NONINVERTINGINPUT\+\_\+\+VP3}~OPAMP\+\_\+\+NONINVERTINGINPUT\+\_\+\+IO3
\item 
\#define {\bfseries OPAMP\+\_\+\+SEC\+\_\+\+NONINVERTINGINPUT\+\_\+\+VP0}~OPAMP\+\_\+\+SEC\+\_\+\+NONINVERTINGINPUT\+\_\+\+IO0
\item 
\#define {\bfseries OPAMP\+\_\+\+SEC\+\_\+\+NONINVERTINGINPUT\+\_\+\+VP1}~OPAMP\+\_\+\+SEC\+\_\+\+NONINVERTINGINPUT\+\_\+\+IO1
\item 
\#define {\bfseries OPAMP\+\_\+\+SEC\+\_\+\+NONINVERTINGINPUT\+\_\+\+VP2}~OPAMP\+\_\+\+SEC\+\_\+\+NONINVERTINGINPUT\+\_\+\+IO2
\item 
\#define {\bfseries OPAMP\+\_\+\+SEC\+\_\+\+NONINVERTINGINPUT\+\_\+\+VP3}~OPAMP\+\_\+\+SEC\+\_\+\+NONINVERTINGINPUT\+\_\+\+IO3
\item 
\#define {\bfseries OPAMP\+\_\+\+INVERTINGINPUT\+\_\+\+VM0}~OPAMP\+\_\+\+INVERTINGINPUT\+\_\+\+IO0
\item 
\#define {\bfseries OPAMP\+\_\+\+INVERTINGINPUT\+\_\+\+VM1}~OPAMP\+\_\+\+INVERTINGINPUT\+\_\+\+IO1
\item 
\#define {\bfseries IOPAMP\+\_\+\+INVERTINGINPUT\+\_\+\+VM0}~OPAMP\+\_\+\+INVERTINGINPUT\+\_\+\+IO0
\item 
\#define {\bfseries IOPAMP\+\_\+\+INVERTINGINPUT\+\_\+\+VM1}~OPAMP\+\_\+\+INVERTINGINPUT\+\_\+\+IO1
\item 
\#define {\bfseries OPAMP\+\_\+\+SEC\+\_\+\+INVERTINGINPUT\+\_\+\+VM0}~OPAMP\+\_\+\+SEC\+\_\+\+INVERTINGINPUT\+\_\+\+IO0
\item 
\#define {\bfseries OPAMP\+\_\+\+SEC\+\_\+\+INVERTINGINPUT\+\_\+\+VM1}~OPAMP\+\_\+\+SEC\+\_\+\+INVERTINGINPUT\+\_\+\+IO1
\item 
\#define {\bfseries OPAMP\+\_\+\+INVERTINGINPUT\+\_\+\+VINM}~OPAMP\+\_\+\+SEC\+\_\+\+INVERTINGINPUT\+\_\+\+IO1
\item 
\#define {\bfseries OPAMP\+\_\+\+PGACONNECT\+\_\+\+NO}~OPAMP\+\_\+\+PGA\+\_\+\+CONNECT\+\_\+\+INVERTINGINPUT\+\_\+\+NO
\item 
\#define {\bfseries OPAMP\+\_\+\+PGACONNECT\+\_\+\+VM0}~OPAMP\+\_\+\+PGA\+\_\+\+CONNECT\+\_\+\+INVERTINGINPUT\+\_\+\+IO0
\item 
\#define {\bfseries OPAMP\+\_\+\+PGACONNECT\+\_\+\+VM1}~OPAMP\+\_\+\+PGA\+\_\+\+CONNECT\+\_\+\+INVERTINGINPUT\+\_\+\+IO1
\item 
\#define {\bfseries I2\+S\+\_\+\+STANDARD\+\_\+\+PHILLIPS}~I2\+S\+\_\+\+STANDARD\+\_\+\+PHILIPS
\item 
\#define {\bfseries CF\+\_\+\+DATA}~ATA\+\_\+\+DATA
\item 
\#define {\bfseries CF\+\_\+\+SECTOR\+\_\+\+COUNT}~ATA\+\_\+\+SECTOR\+\_\+\+COUNT
\item 
\#define {\bfseries CF\+\_\+\+SECTOR\+\_\+\+NUMBER}~ATA\+\_\+\+SECTOR\+\_\+\+NUMBER
\item 
\#define {\bfseries CF\+\_\+\+CYLINDER\+\_\+\+LOW}~ATA\+\_\+\+CYLINDER\+\_\+\+LOW
\item 
\#define {\bfseries CF\+\_\+\+CYLINDER\+\_\+\+HIGH}~ATA\+\_\+\+CYLINDER\+\_\+\+HIGH
\item 
\#define {\bfseries CF\+\_\+\+CARD\+\_\+\+HEAD}~ATA\+\_\+\+CARD\+\_\+\+HEAD
\item 
\#define {\bfseries CF\+\_\+\+STATUS\+\_\+\+CMD}~ATA\+\_\+\+STATUS\+\_\+\+CMD
\item 
\#define {\bfseries CF\+\_\+\+STATUS\+\_\+\+CMD\+\_\+\+ALTERNATE}~ATA\+\_\+\+STATUS\+\_\+\+CMD\+\_\+\+ALTERNATE
\item 
\#define {\bfseries CF\+\_\+\+COMMON\+\_\+\+DATA\+\_\+\+AREA}~ATA\+\_\+\+COMMON\+\_\+\+DATA\+\_\+\+AREA
\item 
\#define {\bfseries CF\+\_\+\+READ\+\_\+\+SECTOR\+\_\+\+CMD}~ATA\+\_\+\+READ\+\_\+\+SECTOR\+\_\+\+CMD
\item 
\#define {\bfseries CF\+\_\+\+WRITE\+\_\+\+SECTOR\+\_\+\+CMD}~ATA\+\_\+\+WRITE\+\_\+\+SECTOR\+\_\+\+CMD
\item 
\#define {\bfseries CF\+\_\+\+ERASE\+\_\+\+SECTOR\+\_\+\+CMD}~ATA\+\_\+\+ERASE\+\_\+\+SECTOR\+\_\+\+CMD
\item 
\#define {\bfseries CF\+\_\+\+IDENTIFY\+\_\+\+CMD}~ATA\+\_\+\+IDENTIFY\+\_\+\+CMD
\item 
\#define {\bfseries PCCARD\+\_\+\+Status\+Typedef}~HAL\+\_\+\+PCCARD\+\_\+\+Status\+Type\+Def
\item 
\#define {\bfseries PCCARD\+\_\+\+SUCCESS}~HAL\+\_\+\+PCCARD\+\_\+\+STATUS\+\_\+\+SUCCESS
\item 
\#define {\bfseries PCCARD\+\_\+\+ONGOING}~HAL\+\_\+\+PCCARD\+\_\+\+STATUS\+\_\+\+ONGOING
\item 
\#define {\bfseries PCCARD\+\_\+\+ERROR}~HAL\+\_\+\+PCCARD\+\_\+\+STATUS\+\_\+\+ERROR
\item 
\#define {\bfseries PCCARD\+\_\+\+TIMEOUT}~HAL\+\_\+\+PCCARD\+\_\+\+STATUS\+\_\+\+TIMEOUT
\item 
\#define {\bfseries FORMAT\+\_\+\+BIN}~RTC\+\_\+\+FORMAT\+\_\+\+BIN
\item 
\#define {\bfseries FORMAT\+\_\+\+BCD}~RTC\+\_\+\+FORMAT\+\_\+\+BCD
\item 
\#define {\bfseries RTC\+\_\+\+ALARMSUBSECONDMASK\+\_\+\+None}~RTC\+\_\+\+ALARMSUBSECONDMASK\+\_\+\+NONE
\item 
\#define {\bfseries RTC\+\_\+\+TAMPERERASEBACKUP\+\_\+\+DISABLED}~RTC\+\_\+\+TAMPER\+\_\+\+ERASE\+\_\+\+BACKUP\+\_\+\+DISABLE
\item 
\#define {\bfseries RTC\+\_\+\+TAMPERMASK\+\_\+\+FLAG\+\_\+\+DISABLED}~RTC\+\_\+\+TAMPERMASK\+\_\+\+FLAG\+\_\+\+DISABLE
\item 
\#define {\bfseries RTC\+\_\+\+TAMPERMASK\+\_\+\+FLAG\+\_\+\+ENABLED}~RTC\+\_\+\+TAMPERMASK\+\_\+\+FLAG\+\_\+\+ENABLE
\item 
\#define {\bfseries RTC\+\_\+\+MASKTAMPERFLAG\+\_\+\+DISABLED}~RTC\+\_\+\+TAMPERMASK\+\_\+\+FLAG\+\_\+\+DISABLE
\item 
\#define {\bfseries RTC\+\_\+\+MASKTAMPERFLAG\+\_\+\+ENABLED}~RTC\+\_\+\+TAMPERMASK\+\_\+\+FLAG\+\_\+\+ENABLE
\item 
\#define {\bfseries RTC\+\_\+\+TAMPERERASEBACKUP\+\_\+\+ENABLED}~RTC\+\_\+\+TAMPER\+\_\+\+ERASE\+\_\+\+BACKUP\+\_\+\+ENABLE
\item 
\#define {\bfseries RTC\+\_\+\+TAMPER1\+\_\+2\+\_\+\+INTERRUPT}~RTC\+\_\+\+ALL\+\_\+\+TAMPER\+\_\+\+INTERRUPT
\item 
\#define {\bfseries RTC\+\_\+\+TAMPER1\+\_\+2\+\_\+3\+\_\+\+INTERRUPT}~RTC\+\_\+\+ALL\+\_\+\+TAMPER\+\_\+\+INTERRUPT
\item 
\#define {\bfseries RTC\+\_\+\+TIMESTAMPPIN\+\_\+\+PC13}~RTC\+\_\+\+TIMESTAMPPIN\+\_\+\+DEFAULT
\item 
\#define {\bfseries RTC\+\_\+\+TIMESTAMPPIN\+\_\+\+PA0}~RTC\+\_\+\+TIMESTAMPPIN\+\_\+\+POS1
\item 
\#define {\bfseries RTC\+\_\+\+TIMESTAMPPIN\+\_\+\+PI8}~RTC\+\_\+\+TIMESTAMPPIN\+\_\+\+POS1
\item 
\#define {\bfseries RTC\+\_\+\+TIMESTAMPPIN\+\_\+\+PC1}~RTC\+\_\+\+TIMESTAMPPIN\+\_\+\+POS2
\item 
\#define {\bfseries RTC\+\_\+\+OUTPUT\+\_\+\+REMAP\+\_\+\+PC13}~RTC\+\_\+\+OUTPUT\+\_\+\+REMAP\+\_\+\+NONE
\item 
\#define {\bfseries RTC\+\_\+\+OUTPUT\+\_\+\+REMAP\+\_\+\+PB14}~RTC\+\_\+\+OUTPUT\+\_\+\+REMAP\+\_\+\+POS1
\item 
\#define {\bfseries RTC\+\_\+\+OUTPUT\+\_\+\+REMAP\+\_\+\+PB2}~RTC\+\_\+\+OUTPUT\+\_\+\+REMAP\+\_\+\+POS1
\item 
\#define {\bfseries RTC\+\_\+\+TAMPERPIN\+\_\+\+PC13}~RTC\+\_\+\+TAMPERPIN\+\_\+\+DEFAULT
\item 
\#define {\bfseries RTC\+\_\+\+TAMPERPIN\+\_\+\+PA0}~RTC\+\_\+\+TAMPERPIN\+\_\+\+POS1
\item 
\#define {\bfseries RTC\+\_\+\+TAMPERPIN\+\_\+\+PI8}~RTC\+\_\+\+TAMPERPIN\+\_\+\+POS1
\item 
\#define {\bfseries SMARTCARD\+\_\+\+NACK\+\_\+\+ENABLED}~SMARTCARD\+\_\+\+NACK\+\_\+\+ENABLE
\item 
\#define {\bfseries SMARTCARD\+\_\+\+NACK\+\_\+\+DISABLED}~SMARTCARD\+\_\+\+NACK\+\_\+\+DISABLE
\item 
\#define {\bfseries SMARTCARD\+\_\+\+ONEBIT\+\_\+\+SAMPLING\+\_\+\+DISABLED}~SMARTCARD\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+DISABLE
\item 
\#define {\bfseries SMARTCARD\+\_\+\+ONEBIT\+\_\+\+SAMPLING\+\_\+\+ENABLED}~SMARTCARD\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+ENABLE
\item 
\#define {\bfseries SMARTCARD\+\_\+\+ONEBIT\+\_\+\+SAMPLING\+\_\+\+DISABLE}~SMARTCARD\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+DISABLE
\item 
\#define {\bfseries SMARTCARD\+\_\+\+ONEBIT\+\_\+\+SAMPLING\+\_\+\+ENABLE}~SMARTCARD\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+ENABLE
\item 
\#define {\bfseries SMARTCARD\+\_\+\+TIMEOUT\+\_\+\+DISABLED}~SMARTCARD\+\_\+\+TIMEOUT\+\_\+\+DISABLE
\item 
\#define {\bfseries SMARTCARD\+\_\+\+TIMEOUT\+\_\+\+ENABLED}~SMARTCARD\+\_\+\+TIMEOUT\+\_\+\+ENABLE
\item 
\#define {\bfseries SMARTCARD\+\_\+\+LASTBIT\+\_\+\+DISABLED}~SMARTCARD\+\_\+\+LASTBIT\+\_\+\+DISABLE
\item 
\#define {\bfseries SMARTCARD\+\_\+\+LASTBIT\+\_\+\+ENABLED}~SMARTCARD\+\_\+\+LASTBIT\+\_\+\+ENABLE
\item 
\#define {\bfseries SMBUS\+\_\+\+DUALADDRESS\+\_\+\+DISABLED}~SMBUS\+\_\+\+DUALADDRESS\+\_\+\+DISABLE
\item 
\#define {\bfseries SMBUS\+\_\+\+DUALADDRESS\+\_\+\+ENABLED}~SMBUS\+\_\+\+DUALADDRESS\+\_\+\+ENABLE
\item 
\#define {\bfseries SMBUS\+\_\+\+GENERALCALL\+\_\+\+DISABLED}~SMBUS\+\_\+\+GENERALCALL\+\_\+\+DISABLE
\item 
\#define {\bfseries SMBUS\+\_\+\+GENERALCALL\+\_\+\+ENABLED}~SMBUS\+\_\+\+GENERALCALL\+\_\+\+ENABLE
\item 
\#define {\bfseries SMBUS\+\_\+\+NOSTRETCH\+\_\+\+DISABLED}~SMBUS\+\_\+\+NOSTRETCH\+\_\+\+DISABLE
\item 
\#define {\bfseries SMBUS\+\_\+\+NOSTRETCH\+\_\+\+ENABLED}~SMBUS\+\_\+\+NOSTRETCH\+\_\+\+ENABLE
\item 
\#define {\bfseries SMBUS\+\_\+\+ANALOGFILTER\+\_\+\+ENABLED}~SMBUS\+\_\+\+ANALOGFILTER\+\_\+\+ENABLE
\item 
\#define {\bfseries SMBUS\+\_\+\+ANALOGFILTER\+\_\+\+DISABLED}~SMBUS\+\_\+\+ANALOGFILTER\+\_\+\+DISABLE
\item 
\#define {\bfseries SMBUS\+\_\+\+PEC\+\_\+\+DISABLED}~SMBUS\+\_\+\+PEC\+\_\+\+DISABLE
\item 
\#define {\bfseries SMBUS\+\_\+\+PEC\+\_\+\+ENABLED}~SMBUS\+\_\+\+PEC\+\_\+\+ENABLE
\item 
\#define {\bfseries HAL\+\_\+\+SMBUS\+\_\+\+STATE\+\_\+\+SLAVE\+\_\+\+LISTEN}~HAL\+\_\+\+SMBUS\+\_\+\+STATE\+\_\+\+LISTEN
\item 
\#define {\bfseries SPI\+\_\+\+TIMODE\+\_\+\+DISABLED}~SPI\+\_\+\+TIMODE\+\_\+\+DISABLE
\item 
\#define {\bfseries SPI\+\_\+\+TIMODE\+\_\+\+ENABLED}~SPI\+\_\+\+TIMODE\+\_\+\+ENABLE
\item 
\#define {\bfseries SPI\+\_\+\+CRCCALCULATION\+\_\+\+DISABLED}~SPI\+\_\+\+CRCCALCULATION\+\_\+\+DISABLE
\item 
\#define {\bfseries SPI\+\_\+\+CRCCALCULATION\+\_\+\+ENABLED}~SPI\+\_\+\+CRCCALCULATION\+\_\+\+ENABLE
\item 
\#define {\bfseries SPI\+\_\+\+NSS\+\_\+\+PULSE\+\_\+\+DISABLED}~SPI\+\_\+\+NSS\+\_\+\+PULSE\+\_\+\+DISABLE
\item 
\#define {\bfseries SPI\+\_\+\+NSS\+\_\+\+PULSE\+\_\+\+ENABLED}~SPI\+\_\+\+NSS\+\_\+\+PULSE\+\_\+\+ENABLE
\item 
\#define {\bfseries CCER\+\_\+\+CCx\+E\+\_\+\+MASK}~TIM\+\_\+\+CCER\+\_\+\+CCx\+E\+\_\+\+MASK
\item 
\#define {\bfseries CCER\+\_\+\+CCx\+NE\+\_\+\+MASK}~TIM\+\_\+\+CCER\+\_\+\+CCx\+NE\+\_\+\+MASK
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CR1}~TIM\+\_\+\+DMABASE\+\_\+\+CR1
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CR2}~TIM\+\_\+\+DMABASE\+\_\+\+CR2
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+SMCR}~TIM\+\_\+\+DMABASE\+\_\+\+SMCR
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+DIER}~TIM\+\_\+\+DMABASE\+\_\+\+DIER
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+SR}~TIM\+\_\+\+DMABASE\+\_\+\+SR
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+EGR}~TIM\+\_\+\+DMABASE\+\_\+\+EGR
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CCMR1}~TIM\+\_\+\+DMABASE\+\_\+\+CCMR1
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CCMR2}~TIM\+\_\+\+DMABASE\+\_\+\+CCMR2
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CCER}~TIM\+\_\+\+DMABASE\+\_\+\+CCER
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CNT}~TIM\+\_\+\+DMABASE\+\_\+\+CNT
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+PSC}~TIM\+\_\+\+DMABASE\+\_\+\+PSC
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+ARR}~TIM\+\_\+\+DMABASE\+\_\+\+ARR
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+RCR}~TIM\+\_\+\+DMABASE\+\_\+\+RCR
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CCR1}~TIM\+\_\+\+DMABASE\+\_\+\+CCR1
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CCR2}~TIM\+\_\+\+DMABASE\+\_\+\+CCR2
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CCR3}~TIM\+\_\+\+DMABASE\+\_\+\+CCR3
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CCR4}~TIM\+\_\+\+DMABASE\+\_\+\+CCR4
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+BDTR}~TIM\+\_\+\+DMABASE\+\_\+\+BDTR
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+DCR}~TIM\+\_\+\+DMABASE\+\_\+\+DCR
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+DMAR}~TIM\+\_\+\+DMABASE\+\_\+\+DMAR
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+OR1}~TIM\+\_\+\+DMABASE\+\_\+\+OR1
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CCMR3}~TIM\+\_\+\+DMABASE\+\_\+\+CCMR3
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CCR5}~TIM\+\_\+\+DMABASE\+\_\+\+CCR5
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+CCR6}~TIM\+\_\+\+DMABASE\+\_\+\+CCR6
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+OR2}~TIM\+\_\+\+DMABASE\+\_\+\+OR2
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+OR3}~TIM\+\_\+\+DMABASE\+\_\+\+OR3
\item 
\#define {\bfseries TIM\+\_\+\+DMABase\+\_\+\+OR}~TIM\+\_\+\+DMABASE\+\_\+\+OR
\item 
\#define {\bfseries TIM\+\_\+\+Event\+Source\+\_\+\+Update}~\mbox{\hyperlink{group___t_i_m___event___source_ga6b9d1352735d2ddbafcaa31ae05cd1ee}{TIM\+\_\+\+EVENTSOURCE\+\_\+\+UPDATE}}
\item 
\#define {\bfseries TIM\+\_\+\+Event\+Source\+\_\+\+CC1}~\mbox{\hyperlink{group___t_i_m___event___source_ga529eadf26cd17108dd95b9707a3d0f55}{TIM\+\_\+\+EVENTSOURCE\+\_\+\+CC1}}
\item 
\#define {\bfseries TIM\+\_\+\+Event\+Source\+\_\+\+CC2}~\mbox{\hyperlink{group___t_i_m___event___source_ga12e3a98c601f4f288354ac2538050e6b}{TIM\+\_\+\+EVENTSOURCE\+\_\+\+CC2}}
\item 
\#define {\bfseries TIM\+\_\+\+Event\+Source\+\_\+\+CC3}~\mbox{\hyperlink{group___t_i_m___event___source_ga1c2faf942ab525b44299ddd0a6d848e4}{TIM\+\_\+\+EVENTSOURCE\+\_\+\+CC3}}
\item 
\#define {\bfseries TIM\+\_\+\+Event\+Source\+\_\+\+CC4}~\mbox{\hyperlink{group___t_i_m___event___source_ga157e43c99e6a1c0097b184cc842b5dfb}{TIM\+\_\+\+EVENTSOURCE\+\_\+\+CC4}}
\item 
\#define {\bfseries TIM\+\_\+\+Event\+Source\+\_\+\+COM}~\mbox{\hyperlink{group___t_i_m___event___source_ga5724ce4aaf842a2166edaaff1531c1d1}{TIM\+\_\+\+EVENTSOURCE\+\_\+\+COM}}
\item 
\#define {\bfseries TIM\+\_\+\+Event\+Source\+\_\+\+Trigger}~\mbox{\hyperlink{group___t_i_m___event___source_ga85573ed76442490db67e4b759fe6d901}{TIM\+\_\+\+EVENTSOURCE\+\_\+\+TRIGGER}}
\item 
\#define {\bfseries TIM\+\_\+\+Event\+Source\+\_\+\+Break}~\mbox{\hyperlink{group___t_i_m___event___source_ga83d16368fe3172a98c41d7c414780a64}{TIM\+\_\+\+EVENTSOURCE\+\_\+\+BREAK}}
\item 
\#define {\bfseries TIM\+\_\+\+Event\+Source\+\_\+\+Break2}~\mbox{\hyperlink{group___t_i_m___event___source_ga1fc597b9937cc1cbc09b0e4450ad55fc}{TIM\+\_\+\+EVENTSOURCE\+\_\+\+BREAK2}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+1\+Transfer}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_ga74f07b4a10022d71f31ec6e1b2b69276}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+1\+TRANSFER}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+2\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_gab114592091a00e0a6b9ae464485bd7bb}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+2\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+3\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_gad91c14f0930803593ecdbd98002fea0a}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+3\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+4\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_ga9ada9605ae6ff6e4ada9701263bef812}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+4\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+5\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_ga740a6446c0a517cc3e235fddee45fef5}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+5\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+6\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_ga905c206d2a028e3fb92bcab8f9f7c869}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+6\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+7\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_gae75055ac13b73baf9326f1d6157853a7}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+7\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+8\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_gac6b24f5b7d9e1968b4bfcaeb24e718fc}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+8\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+9\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_ga73fff75a3f0247c61a84a42e8cb83572}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+9\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+10\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_ga793a89bb8a0669e274de451985186c53}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+10\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+11\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_ga79ab58b6a3b30c54c0758b381df22cb0}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+11\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+12\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_gaf52962b501b3a76d89df6274ed425947}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+12\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+13\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_ga06a81eba628bea6495d86ebcc6021da0}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+13\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+14\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_ga5f430b76c0aeded0a8d8be779f26ae52}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+14\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+15\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_ga98a4d88c533178bc1b4347e4c5ce815a}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+15\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+16\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_gaf4b2a1fe12c52272544c21e17de1ed90}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+16\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+17\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_gad31c1fca7ed436a53efc4f290144584d}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+17\+TRANSFERS}}
\item 
\#define {\bfseries TIM\+\_\+\+DMABurst\+Length\+\_\+18\+Transfers}~\mbox{\hyperlink{group___t_i_m___d_m_a___burst___length_gabb6f72b02ee1c8855de241cb0713e2ca}{TIM\+\_\+\+DMABURSTLENGTH\+\_\+18\+TRANSFERS}}
\item 
\#define {\bfseries TSC\+\_\+\+SYNC\+\_\+\+POL\+\_\+\+FALL}~TSC\+\_\+\+SYNC\+\_\+\+POLARITY\+\_\+\+FALLING
\item 
\#define {\bfseries TSC\+\_\+\+SYNC\+\_\+\+POL\+\_\+\+RISE\+\_\+\+HIGH}~TSC\+\_\+\+SYNC\+\_\+\+POLARITY\+\_\+\+RISING
\item 
\#define {\bfseries UART\+\_\+\+ONEBIT\+\_\+\+SAMPLING\+\_\+\+DISABLED}~\mbox{\hyperlink{group___u_a_r_t___one_bit___sampling_gadfcb0e9db2719321048b249b2c5cc15f}{UART\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+DISABLE}}
\item 
\#define {\bfseries UART\+\_\+\+ONEBIT\+\_\+\+SAMPLING\+\_\+\+ENABLED}~\mbox{\hyperlink{group___u_a_r_t___one_bit___sampling_gadcc0aed6e7a466da3c45363f69dcbfb6}{UART\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+ENABLE}}
\item 
\#define {\bfseries UART\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+DISABLED}~\mbox{\hyperlink{group___u_a_r_t___one_bit___sampling_gadfcb0e9db2719321048b249b2c5cc15f}{UART\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+DISABLE}}
\item 
\#define {\bfseries UART\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+ENABLED}~\mbox{\hyperlink{group___u_a_r_t___one_bit___sampling_gadcc0aed6e7a466da3c45363f69dcbfb6}{UART\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UART\+\_\+\+ONEBIT\+\_\+\+ENABLE}~\mbox{\hyperlink{group___u_a_r_t___exported___macros_ga3524747e5896296ab066d786431503ce}{\+\_\+\+\_\+\+HAL\+\_\+\+UART\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UART\+\_\+\+ONEBIT\+\_\+\+DISABLE}~\mbox{\hyperlink{group___u_a_r_t___exported___macros_ga2dbd7e6592e8c5999f817b69f0fd24bb}{\+\_\+\+\_\+\+HAL\+\_\+\+UART\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE\+\_\+\+DISABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+DIV\+\_\+\+SAMPLING16}~\mbox{\hyperlink{group___u_a_r_t___private___macros_ga5321c542a31ad6a0dff145a71e55c1c2}{UART\+\_\+\+DIV\+\_\+\+SAMPLING16}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+DIVMANT\+\_\+\+SAMPLING16}~UART\+\_\+\+DIVMANT\+\_\+\+SAMPLING16
\item 
\#define {\bfseries \+\_\+\+\_\+\+DIVFRAQ\+\_\+\+SAMPLING16}~UART\+\_\+\+DIVFRAQ\+\_\+\+SAMPLING16
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART\+\_\+\+BRR\+\_\+\+SAMPLING16}~UART\+\_\+\+BRR\+\_\+\+SAMPLING16
\item 
\#define {\bfseries \+\_\+\+\_\+\+DIV\+\_\+\+SAMPLING8}~\mbox{\hyperlink{group___u_a_r_t___private___macros_gae18b02b9da2d07b28bfc070fec4225a4}{UART\+\_\+\+DIV\+\_\+\+SAMPLING8}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+DIVMANT\+\_\+\+SAMPLING8}~UART\+\_\+\+DIVMANT\+\_\+\+SAMPLING8
\item 
\#define {\bfseries \+\_\+\+\_\+\+DIVFRAQ\+\_\+\+SAMPLING8}~UART\+\_\+\+DIVFRAQ\+\_\+\+SAMPLING8
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART\+\_\+\+BRR\+\_\+\+SAMPLING8}~UART\+\_\+\+BRR\+\_\+\+SAMPLING8
\item 
\#define {\bfseries \+\_\+\+\_\+\+DIV\+\_\+\+LPUART}~\mbox{\hyperlink{group___u_a_r_t___private___macros_gacdbf9c41318d542f8fe3841d6981e89f}{UART\+\_\+\+DIV\+\_\+\+LPUART}}
\item 
\#define {\bfseries UART\+\_\+\+WAKEUPMETHODE\+\_\+\+IDLELINE}~\mbox{\hyperlink{group___u_a_r_t___wake_up___methods_ga2411ed44c5d82db84c5819e1e2b5b8b3}{UART\+\_\+\+WAKEUPMETHOD\+\_\+\+IDLELINE}}
\item 
\#define {\bfseries UART\+\_\+\+WAKEUPMETHODE\+\_\+\+ADDRESSMARK}~\mbox{\hyperlink{group___u_a_r_t___wake_up___methods_ga4c6935f26f8f2a9fe70fd6306a9882cb}{UART\+\_\+\+WAKEUPMETHOD\+\_\+\+ADDRESSMARK}}
\item 
\#define {\bfseries USART\+\_\+\+CLOCK\+\_\+\+DISABLED}~USART\+\_\+\+CLOCK\+\_\+\+DISABLE
\item 
\#define {\bfseries USART\+\_\+\+CLOCK\+\_\+\+ENABLED}~USART\+\_\+\+CLOCK\+\_\+\+ENABLE
\item 
\#define {\bfseries USARTNACK\+\_\+\+ENABLED}~USART\+\_\+\+NACK\+\_\+\+ENABLE
\item 
\#define {\bfseries USARTNACK\+\_\+\+DISABLED}~USART\+\_\+\+NACK\+\_\+\+DISABLE
\item 
\#define {\bfseries CFR\+\_\+\+BASE}~WWDG\+\_\+\+CFR\+\_\+\+BASE
\item 
\#define {\bfseries CAN\+\_\+\+Filter\+FIFO0}~CAN\+\_\+\+FILTER\+\_\+\+FIFO0
\item 
\#define {\bfseries CAN\+\_\+\+Filter\+FIFO1}~CAN\+\_\+\+FILTER\+\_\+\+FIFO1
\item 
\#define {\bfseries CAN\+\_\+\+IT\+\_\+\+RQCP0}~CAN\+\_\+\+IT\+\_\+\+TME
\item 
\#define {\bfseries CAN\+\_\+\+IT\+\_\+\+RQCP1}~CAN\+\_\+\+IT\+\_\+\+TME
\item 
\#define {\bfseries CAN\+\_\+\+IT\+\_\+\+RQCP2}~CAN\+\_\+\+IT\+\_\+\+TME
\item 
\#define {\bfseries INAK\+\_\+\+TIMEOUT}~CAN\+\_\+\+TIMEOUT\+\_\+\+VALUE
\item 
\#define {\bfseries SLAK\+\_\+\+TIMEOUT}~CAN\+\_\+\+TIMEOUT\+\_\+\+VALUE
\item 
\#define {\bfseries CAN\+\_\+\+TXSTATUS\+\_\+\+FAILED}~((uint8\+\_\+t)0x00U)
\item 
\#define {\bfseries CAN\+\_\+\+TXSTATUS\+\_\+\+OK}~((uint8\+\_\+t)0x01U)
\item 
\#define {\bfseries CAN\+\_\+\+TXSTATUS\+\_\+\+PENDING}~((uint8\+\_\+t)0x02U)
\item 
\#define {\bfseries VLAN\+\_\+\+TAG}~ETH\+\_\+\+VLAN\+\_\+\+TAG
\item 
\#define {\bfseries MIN\+\_\+\+ETH\+\_\+\+PAYLOAD}~ETH\+\_\+\+MIN\+\_\+\+ETH\+\_\+\+PAYLOAD
\item 
\#define {\bfseries MAX\+\_\+\+ETH\+\_\+\+PAYLOAD}~ETH\+\_\+\+MAX\+\_\+\+ETH\+\_\+\+PAYLOAD
\item 
\#define {\bfseries JUMBO\+\_\+\+FRAME\+\_\+\+PAYLOAD}~ETH\+\_\+\+JUMBO\+\_\+\+FRAME\+\_\+\+PAYLOAD
\item 
\#define {\bfseries MACMIIAR\+\_\+\+CR\+\_\+\+MASK}~ETH\+\_\+\+MACMIIAR\+\_\+\+CR\+\_\+\+MASK
\item 
\#define {\bfseries MACCR\+\_\+\+CLEAR\+\_\+\+MASK}~ETH\+\_\+\+MACCR\+\_\+\+CLEAR\+\_\+\+MASK
\item 
\#define {\bfseries MACFCR\+\_\+\+CLEAR\+\_\+\+MASK}~ETH\+\_\+\+MACFCR\+\_\+\+CLEAR\+\_\+\+MASK
\item 
\#define {\bfseries DMAOMR\+\_\+\+CLEAR\+\_\+\+MASK}~ETH\+\_\+\+DMAOMR\+\_\+\+CLEAR\+\_\+\+MASK
\item 
\#define {\bfseries ETH\+\_\+\+MMCCR}~0x00000100U
\item 
\#define {\bfseries ETH\+\_\+\+MMCRIR}~0x00000104U
\item 
\#define {\bfseries ETH\+\_\+\+MMCTIR}~0x00000108U
\item 
\#define {\bfseries ETH\+\_\+\+MMCRIMR}~0x0000010\+CU
\item 
\#define {\bfseries ETH\+\_\+\+MMCTIMR}~0x00000110U
\item 
\#define {\bfseries ETH\+\_\+\+MMCTGFSCCR}~0x0000014\+CU
\item 
\#define {\bfseries ETH\+\_\+\+MMCTGFMSCCR}~0x00000150U
\item 
\#define {\bfseries ETH\+\_\+\+MMCTGFCR}~0x00000168U
\item 
\#define {\bfseries ETH\+\_\+\+MMCRFCECR}~0x00000194U
\item 
\#define {\bfseries ETH\+\_\+\+MMCRFAECR}~0x00000198U
\item 
\#define {\bfseries ETH\+\_\+\+MMCRGUFCR}~0x000001\+C4U
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+TXFIFO\+\_\+\+FULL}~0x02000000U  /\texorpdfstring{$\ast$}{*} Tx FIFO full \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+TXFIFONOT\+\_\+\+EMPTY}~0x01000000U  /\texorpdfstring{$\ast$}{*} Tx FIFO not empty \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+TXFIFO\+\_\+\+WRITE\+\_\+\+ACTIVE}~0x00400000U  /\texorpdfstring{$\ast$}{*} Tx FIFO write active \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+TXFIFO\+\_\+\+IDLE}~0x00000000U  /\texorpdfstring{$\ast$}{*} Tx FIFO read status\+: Idle \texorpdfstring{$\ast$}{*}/
\item 
\#define \mbox{\hyperlink{group___h_a_l___e_t_h___aliased___defines_ga162f3eb163f0fc63e0ef21f640ee3b35}{ETH\+\_\+\+MAC\+\_\+\+TXFIFO\+\_\+\+READ}}
\item 
\#define \mbox{\hyperlink{group___h_a_l___e_t_h___aliased___defines_ga732d203562136a49e6fdfe08cbbdb007}{ETH\+\_\+\+MAC\+\_\+\+TXFIFO\+\_\+\+WAITING}}
\item 
\#define \mbox{\hyperlink{group___h_a_l___e_t_h___aliased___defines_gaa98e266d20386f08f1e7d07924ae7fd8}{ETH\+\_\+\+MAC\+\_\+\+TXFIFO\+\_\+\+WRITING}}
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+TRANSMISSION\+\_\+\+PAUSE}~0x00080000U  /\texorpdfstring{$\ast$}{*} MAC transmitter in pause \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+TRANSMITFRAMECONTROLLER\+\_\+\+IDLE}~0x00000000U  /\texorpdfstring{$\ast$}{*} MAC transmit frame controller\+: Idle \texorpdfstring{$\ast$}{*}/
\item 
\#define \mbox{\hyperlink{group___h_a_l___e_t_h___aliased___defines_ga51af5af4f0244add557e29f1c1085c76}{ETH\+\_\+\+MAC\+\_\+\+TRANSMITFRAMECONTROLLER\+\_\+\+WAITING}}
\item 
\#define \mbox{\hyperlink{group___h_a_l___e_t_h___aliased___defines_ga30f5421c685cc87345a62034f03e9ede}{ETH\+\_\+\+MAC\+\_\+\+TRANSMITFRAMECONTROLLER\+\_\+\+GENRATING\+\_\+\+PCF}}
\item 
\#define \mbox{\hyperlink{group___h_a_l___e_t_h___aliased___defines_ga813acc11409391a70e9c8f4e2c769cf1}{ETH\+\_\+\+MAC\+\_\+\+TRANSMITFRAMECONTROLLER\+\_\+\+TRANSFERRING}}
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+MII\+\_\+\+TRANSMIT\+\_\+\+ACTIVE}~0x00010000U  /\texorpdfstring{$\ast$}{*} MAC MII transmit engine active \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+RXFIFO\+\_\+\+EMPTY}~0x00000000U  /\texorpdfstring{$\ast$}{*} Rx FIFO fill level\+: empty \texorpdfstring{$\ast$}{*}/
\item 
\#define \mbox{\hyperlink{group___h_a_l___e_t_h___aliased___defines_ga1ac34f74c22709a45510fe557e6b1866}{ETH\+\_\+\+MAC\+\_\+\+RXFIFO\+\_\+\+BELOW\+\_\+\+THRESHOLD}}
\item 
\#define \mbox{\hyperlink{group___h_a_l___e_t_h___aliased___defines_ga10d4ac5728fe85efe0ec19699e4c90f0}{ETH\+\_\+\+MAC\+\_\+\+RXFIFO\+\_\+\+ABOVE\+\_\+\+THRESHOLD}}
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+RXFIFO\+\_\+\+FULL}~0x00000300U  /\texorpdfstring{$\ast$}{*} Rx FIFO fill level\+: full \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+READCONTROLLER\+\_\+\+IDLE}~0x00000000U  /\texorpdfstring{$\ast$}{*} Rx FIFO read controller IDLE state \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+READCONTROLLER\+\_\+\+READING\+\_\+\+DATA}~0x00000020U  /\texorpdfstring{$\ast$}{*} Rx FIFO read controller Reading frame data \texorpdfstring{$\ast$}{*}/
\item 
\#define \mbox{\hyperlink{group___h_a_l___e_t_h___aliased___defines_ga441228e7ee2416d37f22f5081d739e2c}{ETH\+\_\+\+MAC\+\_\+\+READCONTROLLER\+\_\+\+READING\+\_\+\+STATUS}}
\item 
\#define \mbox{\hyperlink{group___h_a_l___e_t_h___aliased___defines_ga7a4fe56723328085b9b80adbfb528a5d}{ETH\+\_\+\+MAC\+\_\+\+READCONTROLLER\+\_\+\+FLUSHING}}
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+RXFIFO\+\_\+\+WRITE\+\_\+\+ACTIVE}~0x00000010U  /\texorpdfstring{$\ast$}{*} Rx FIFO write controller active \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+SMALL\+\_\+\+FIFO\+\_\+\+NOTACTIVE}~0x00000000U  /\texorpdfstring{$\ast$}{*} MAC small FIFO read / write controllers not active \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+SMALL\+\_\+\+FIFO\+\_\+\+READ\+\_\+\+ACTIVE}~0x00000002U  /\texorpdfstring{$\ast$}{*} MAC small FIFO read controller active \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+SMALL\+\_\+\+FIFO\+\_\+\+WRITE\+\_\+\+ACTIVE}~0x00000004U  /\texorpdfstring{$\ast$}{*} MAC small FIFO write controller active \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+SMALL\+\_\+\+FIFO\+\_\+\+RW\+\_\+\+ACTIVE}~0x00000006U  /\texorpdfstring{$\ast$}{*} MAC small FIFO read / write controllers active \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+MAC\+\_\+\+MII\+\_\+\+RECEIVE\+\_\+\+PROTOCOL\+\_\+\+ACTIVE}~0x00000001U  /\texorpdfstring{$\ast$}{*} MAC MII receive protocol engine active \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries ETH\+\_\+\+Tx\+Packet\+Config}~ETH\+\_\+\+Tx\+Packet\+Config\+Type\+Def   /\texorpdfstring{$\ast$}{*} Transmit Packet Configuration structure definition \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries HAL\+\_\+\+DCMI\+\_\+\+ERROR\+\_\+\+OVF}~HAL\+\_\+\+DCMI\+\_\+\+ERROR\+\_\+\+OVR
\item 
\#define {\bfseries DCMI\+\_\+\+IT\+\_\+\+OVF}~DCMI\+\_\+\+IT\+\_\+\+OVR
\item 
\#define {\bfseries DCMI\+\_\+\+FLAG\+\_\+\+OVFRI}~DCMI\+\_\+\+FLAG\+\_\+\+OVRRI
\item 
\#define {\bfseries DCMI\+\_\+\+FLAG\+\_\+\+OVFMI}~DCMI\+\_\+\+FLAG\+\_\+\+OVRMI
\item 
\#define {\bfseries HAL\+\_\+\+DCMI\+\_\+\+Config\+CROP}~HAL\+\_\+\+DCMI\+\_\+\+Config\+Crop
\item 
\#define {\bfseries HAL\+\_\+\+DCMI\+\_\+\+Enable\+CROP}~HAL\+\_\+\+DCMI\+\_\+\+Enable\+Crop
\item 
\#define {\bfseries HAL\+\_\+\+DCMI\+\_\+\+Disable\+CROP}~HAL\+\_\+\+DCMI\+\_\+\+Disable\+Crop
\item 
\#define {\bfseries HAL\+\_\+\+CRYP\+\_\+\+Computation\+Cplt\+Callback}~HAL\+\_\+\+CRYPEx\+\_\+\+Computation\+Cplt\+Callback
\item 
\#define \mbox{\hyperlink{group___h_a_s_h__alias_ga07f5e403a49f9a7fa39ddc2a13a13f9a}{HAL\+\_\+\+HASHEx\+\_\+\+IRQHandler}}~HAL\+\_\+\+HASH\+\_\+\+IRQHandler
\item 
\#define {\bfseries HAL\+\_\+\+HASH\+\_\+\+STATEType\+Def}~HAL\+\_\+\+HASH\+\_\+\+State\+Type\+Def
\item 
\#define {\bfseries HAL\+\_\+\+HASHPhase\+Type\+Def}~HAL\+\_\+\+HASH\+\_\+\+Phase\+Type\+Def
\item 
\#define {\bfseries HAL\+\_\+\+HMAC\+\_\+\+MD5\+\_\+\+Finish}~HAL\+\_\+\+HASH\+\_\+\+MD5\+\_\+\+Finish
\item 
\#define {\bfseries HAL\+\_\+\+HMAC\+\_\+\+SHA1\+\_\+\+Finish}~HAL\+\_\+\+HASH\+\_\+\+SHA1\+\_\+\+Finish
\item 
\#define {\bfseries HAL\+\_\+\+HMAC\+\_\+\+SHA224\+\_\+\+Finish}~HAL\+\_\+\+HASH\+\_\+\+SHA224\+\_\+\+Finish
\item 
\#define {\bfseries HAL\+\_\+\+HMAC\+\_\+\+SHA256\+\_\+\+Finish}~HAL\+\_\+\+HASH\+\_\+\+SHA256\+\_\+\+Finish
\item 
\#define {\bfseries HASH\+\_\+\+Algo\+Selection\+\_\+\+SHA1}~HASH\+\_\+\+ALGOSELECTION\+\_\+\+SHA1
\item 
\#define {\bfseries HASH\+\_\+\+Algo\+Selection\+\_\+\+SHA224}~HASH\+\_\+\+ALGOSELECTION\+\_\+\+SHA224
\item 
\#define {\bfseries HASH\+\_\+\+Algo\+Selection\+\_\+\+SHA256}~HASH\+\_\+\+ALGOSELECTION\+\_\+\+SHA256
\item 
\#define {\bfseries HASH\+\_\+\+Algo\+Selection\+\_\+\+MD5}~HASH\+\_\+\+ALGOSELECTION\+\_\+\+MD5
\item 
\#define {\bfseries HASH\+\_\+\+Algo\+Mode\+\_\+\+HASH}~HASH\+\_\+\+ALGOMODE\+\_\+\+HASH
\item 
\#define {\bfseries HASH\+\_\+\+Algo\+Mode\+\_\+\+HMAC}~HASH\+\_\+\+ALGOMODE\+\_\+\+HMAC
\item 
\#define {\bfseries HASH\+\_\+\+HMACKey\+Type\+\_\+\+Short\+Key}~HASH\+\_\+\+HMAC\+\_\+\+KEYTYPE\+\_\+\+SHORTKEY
\item 
\#define {\bfseries HASH\+\_\+\+HMACKey\+Type\+\_\+\+Long\+Key}~HASH\+\_\+\+HMAC\+\_\+\+KEYTYPE\+\_\+\+LONGKEY
\item 
\#define {\bfseries HAL\+\_\+\+Enable\+DBGSleep\+Mode}~\mbox{\hyperlink{group___h_a_l___exported___functions_gaf031bcc71ebad9b7edf405547efd762b}{HAL\+\_\+\+DBGMCU\+\_\+\+Enable\+DBGSleep\+Mode}}
\item 
\#define {\bfseries HAL\+\_\+\+Disable\+DBGSleep\+Mode}~\mbox{\hyperlink{group___h_a_l___exported___functions_gac7820d0561f19999a68d714655b901b5}{HAL\+\_\+\+DBGMCU\+\_\+\+Disable\+DBGSleep\+Mode}}
\item 
\#define {\bfseries HAL\+\_\+\+Enable\+DBGStop\+Mode}~\mbox{\hyperlink{group___h_a_l___exported___functions_gadf25043b17de4bef38a95a75fd03e5c4}{HAL\+\_\+\+DBGMCU\+\_\+\+Enable\+DBGStop\+Mode}}
\item 
\#define {\bfseries HAL\+\_\+\+Disable\+DBGStop\+Mode}~\mbox{\hyperlink{group___h_a_l___exported___functions_ga2c93dcee35e5983d74f1000de7c042d5}{HAL\+\_\+\+DBGMCU\+\_\+\+Disable\+DBGStop\+Mode}}
\item 
\#define {\bfseries HAL\+\_\+\+Enable\+DBGStandby\+Mode}~\mbox{\hyperlink{group___h_a_l___exported___functions_ga28a1323b2eeb0a408c1cfdbfa0db5ead}{HAL\+\_\+\+DBGMCU\+\_\+\+Enable\+DBGStandby\+Mode}}
\item 
\#define {\bfseries HAL\+\_\+\+Disable\+DBGStandby\+Mode}~\mbox{\hyperlink{group___h_a_l___exported___functions_ga7faa58d8508ea3123b9f247a70379779}{HAL\+\_\+\+DBGMCU\+\_\+\+Disable\+DBGStandby\+Mode}}
\item 
\#define \mbox{\hyperlink{group___h_a_l___aliased___functions_gaeece8fd3268534ce330c635222ce79a3}{HAL\+\_\+\+DBG\+\_\+\+Low\+Power\+Config}}(Periph,  cmd)
\item 
\#define {\bfseries HAL\+\_\+\+VREFINT\+\_\+\+Output\+Select}~HAL\+\_\+\+SYSCFG\+\_\+\+VREFINT\+\_\+\+Output\+Select
\item 
\#define \mbox{\hyperlink{group___h_a_l___aliased___functions_ga72384357565be710258691efd3b3b72c}{HAL\+\_\+\+Lock\+\_\+\+Cmd}}(cmd)
\item 
\#define \mbox{\hyperlink{group___h_a_l___aliased___functions_ga89195eed3652b3f7ce36e89f3cc8e3a6}{HAL\+\_\+\+VREFINT\+\_\+\+Cmd}}(cmd)
\item 
\#define \mbox{\hyperlink{group___h_a_l___aliased___functions_ga2945c26e7b184a3ee89309906de33cd3}{HAL\+\_\+\+ADC\+\_\+\+Enable\+Buffer\+\_\+\+Cmd}}(cmd)
\item 
\#define \mbox{\hyperlink{group___h_a_l___aliased___functions_ga674bce235a7be59ff19cca605b2e3ce8}{HAL\+\_\+\+ADC\+\_\+\+Enable\+Buffer\+Sensor\+\_\+\+Cmd}}(cmd)
\item 
\#define {\bfseries FLASH\+\_\+\+Half\+Page\+Program}~HAL\+\_\+\+FLASHEx\+\_\+\+Half\+Page\+Program
\item 
\#define {\bfseries FLASH\+\_\+\+Enable\+Run\+Power\+Down}~HAL\+\_\+\+FLASHEx\+\_\+\+Enable\+Run\+Power\+Down
\item 
\#define {\bfseries FLASH\+\_\+\+Disable\+Run\+Power\+Down}~HAL\+\_\+\+FLASHEx\+\_\+\+Disable\+Run\+Power\+Down
\item 
\#define {\bfseries HAL\+\_\+\+DATA\+\_\+\+EEPROMEx\+\_\+\+Unlock}~HAL\+\_\+\+FLASHEx\+\_\+\+DATAEEPROM\+\_\+\+Unlock
\item 
\#define {\bfseries HAL\+\_\+\+DATA\+\_\+\+EEPROMEx\+\_\+\+Lock}~HAL\+\_\+\+FLASHEx\+\_\+\+DATAEEPROM\+\_\+\+Lock
\item 
\#define {\bfseries HAL\+\_\+\+DATA\+\_\+\+EEPROMEx\+\_\+\+Erase}~HAL\+\_\+\+FLASHEx\+\_\+\+DATAEEPROM\+\_\+\+Erase
\item 
\#define {\bfseries HAL\+\_\+\+DATA\+\_\+\+EEPROMEx\+\_\+\+Program}~HAL\+\_\+\+FLASHEx\+\_\+\+DATAEEPROM\+\_\+\+Program
\item 
\#define {\bfseries HAL\+\_\+\+I2\+CEx\+\_\+\+Analog\+Filter\+\_\+\+Config}~HAL\+\_\+\+I2\+CEx\+\_\+\+Config\+Analog\+Filter
\item 
\#define {\bfseries HAL\+\_\+\+I2\+CEx\+\_\+\+Digital\+Filter\+\_\+\+Config}~HAL\+\_\+\+I2\+CEx\+\_\+\+Config\+Digital\+Filter
\item 
\#define {\bfseries HAL\+\_\+\+FMPI2\+CEx\+\_\+\+Analog\+Filter\+\_\+\+Config}~HAL\+\_\+\+FMPI2\+CEx\+\_\+\+Config\+Analog\+Filter
\item 
\#define {\bfseries HAL\+\_\+\+FMPI2\+CEx\+\_\+\+Digital\+Filter\+\_\+\+Config}~HAL\+\_\+\+FMPI2\+CEx\+\_\+\+Config\+Digital\+Filter
\item 
\#define \mbox{\hyperlink{group___h_a_l___i2_c___aliased___functions_ga340e0d97db96b108c18718d4b37bdb29}{HAL\+\_\+\+I2\+CFast\+Mode\+Plus\+Config}}(SYSCFG\+\_\+\+I2\+CFast\+Mode\+Plus,  cmd)
\item 
\#define {\bfseries HAL\+\_\+\+PWR\+\_\+\+PVDConfig}~HAL\+\_\+\+PWR\+\_\+\+Config\+PVD
\item 
\#define {\bfseries HAL\+\_\+\+PWR\+\_\+\+Disable\+Bk\+Up\+Reg}~HAL\+\_\+\+PWREx\+\_\+\+Disable\+Bk\+Up\+Reg
\item 
\#define {\bfseries HAL\+\_\+\+PWR\+\_\+\+Disable\+Flash\+Power\+Down}~HAL\+\_\+\+PWREx\+\_\+\+Disable\+Flash\+Power\+Down
\item 
\#define {\bfseries HAL\+\_\+\+PWR\+\_\+\+Disable\+Vddio2\+Monitor}~HAL\+\_\+\+PWREx\+\_\+\+Disable\+Vddio2\+Monitor
\item 
\#define {\bfseries HAL\+\_\+\+PWR\+\_\+\+Enable\+Bk\+Up\+Reg}~HAL\+\_\+\+PWREx\+\_\+\+Enable\+Bk\+Up\+Reg
\item 
\#define {\bfseries HAL\+\_\+\+PWR\+\_\+\+Enable\+Flash\+Power\+Down}~HAL\+\_\+\+PWREx\+\_\+\+Enable\+Flash\+Power\+Down
\item 
\#define {\bfseries HAL\+\_\+\+PWR\+\_\+\+Enable\+Vddio2\+Monitor}~HAL\+\_\+\+PWREx\+\_\+\+Enable\+Vddio2\+Monitor
\item 
\#define {\bfseries HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+PVM\+\_\+\+IRQHandler}~HAL\+\_\+\+PWREx\+\_\+\+PVD\+\_\+\+PVM\+\_\+\+IRQHandler
\item 
\#define {\bfseries HAL\+\_\+\+PWR\+\_\+\+PVDLevel\+Config}~HAL\+\_\+\+PWR\+\_\+\+Config\+PVD
\item 
\#define {\bfseries HAL\+\_\+\+PWR\+\_\+\+Vddio2\+Monitor\+\_\+\+IRQHandler}~HAL\+\_\+\+PWREx\+\_\+\+Vddio2\+Monitor\+\_\+\+IRQHandler
\item 
\#define {\bfseries HAL\+\_\+\+PWR\+\_\+\+Vddio2\+Monitor\+Callback}~HAL\+\_\+\+PWREx\+\_\+\+Vddio2\+Monitor\+Callback
\item 
\#define {\bfseries HAL\+\_\+\+PWREx\+\_\+\+Activate\+Over\+Drive}~HAL\+\_\+\+PWREx\+\_\+\+Enable\+Over\+Drive
\item 
\#define {\bfseries HAL\+\_\+\+PWREx\+\_\+\+Deactivate\+Over\+Drive}~HAL\+\_\+\+PWREx\+\_\+\+Disable\+Over\+Drive
\item 
\#define {\bfseries HAL\+\_\+\+PWREx\+\_\+\+Disable\+SDADCAnalog}~HAL\+\_\+\+PWREx\+\_\+\+Disable\+SDADC
\item 
\#define {\bfseries HAL\+\_\+\+PWREx\+\_\+\+Enable\+SDADCAnalog}~HAL\+\_\+\+PWREx\+\_\+\+Enable\+SDADC
\item 
\#define {\bfseries HAL\+\_\+\+PWREx\+\_\+\+PVMConfig}~HAL\+\_\+\+PWREx\+\_\+\+Config\+PVM
\item 
\#define {\bfseries PWR\+\_\+\+MODE\+\_\+\+NORMAL}~\mbox{\hyperlink{group___p_w_r___p_v_d___mode_ga3a4bf701a36a14a4edf4dc5a28153277}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+NORMAL}}
\item 
\#define {\bfseries PWR\+\_\+\+MODE\+\_\+\+IT\+\_\+\+RISING}~\mbox{\hyperlink{group___p_w_r___p_v_d___mode_ga102d7b8354419990a2a780f61cd020a6}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+IT\+\_\+\+RISING}}
\item 
\#define {\bfseries PWR\+\_\+\+MODE\+\_\+\+IT\+\_\+\+FALLING}~\mbox{\hyperlink{group___p_w_r___p_v_d___mode_gab600a54f3a588de836cfe4b727ab8a53}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+IT\+\_\+\+FALLING}}
\item 
\#define {\bfseries PWR\+\_\+\+MODE\+\_\+\+IT\+\_\+\+RISING\+\_\+\+FALLING}~\mbox{\hyperlink{group___p_w_r___p_v_d___mode_gac531fbf14457e6595505354fad521b67}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+IT\+\_\+\+RISING\+\_\+\+FALLING}}
\item 
\#define {\bfseries PWR\+\_\+\+MODE\+\_\+\+EVENT\+\_\+\+RISING}~\mbox{\hyperlink{group___p_w_r___p_v_d___mode_ga1a946b01887aa886de329a92c3ab0dd4}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+EVENT\+\_\+\+RISING}}
\item 
\#define {\bfseries PWR\+\_\+\+MODE\+\_\+\+EVENT\+\_\+\+FALLING}~\mbox{\hyperlink{group___p_w_r___p_v_d___mode_gaaedbe45f1a1ea6c30af6ac51abae0cae}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+EVENT\+\_\+\+FALLING}}
\item 
\#define {\bfseries PWR\+\_\+\+MODE\+\_\+\+EVENT\+\_\+\+RISING\+\_\+\+FALLING}~\mbox{\hyperlink{group___p_w_r___p_v_d___mode_ga7455387c8e9049f9f66b46423d4f4091}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+EVENT\+\_\+\+RISING\+\_\+\+FALLING}}
\item 
\#define {\bfseries CR\+\_\+\+OFFSET\+\_\+\+BB}~PWR\+\_\+\+CR\+\_\+\+OFFSET\+\_\+\+BB
\item 
\#define {\bfseries CSR\+\_\+\+OFFSET\+\_\+\+BB}~PWR\+\_\+\+CSR\+\_\+\+OFFSET\+\_\+\+BB
\item 
\#define {\bfseries PMODE\+\_\+\+BIT\+\_\+\+NUMBER}~VOS\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries CR\+\_\+\+PMODE\+\_\+\+BB}~CR\+\_\+\+VOS\+\_\+\+BB
\item 
\#define {\bfseries DBP\+\_\+\+Bit\+Number}~DBP\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries PVDE\+\_\+\+Bit\+Number}~PVDE\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries PMODE\+\_\+\+Bit\+Number}~PMODE\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries EWUP\+\_\+\+Bit\+Number}~EWUP\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries FPDS\+\_\+\+Bit\+Number}~FPDS\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries ODEN\+\_\+\+Bit\+Number}~ODEN\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries ODSWEN\+\_\+\+Bit\+Number}~ODSWEN\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries MRLVDS\+\_\+\+Bit\+Number}~MRLVDS\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries LPLVDS\+\_\+\+Bit\+Number}~LPLVDS\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries BRE\+\_\+\+Bit\+Number}~BRE\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries PWR\+\_\+\+MODE\+\_\+\+EVT}~\mbox{\hyperlink{group___p_w_r___p_v_d___mode_ga3a4bf701a36a14a4edf4dc5a28153277}{PWR\+\_\+\+PVD\+\_\+\+MODE\+\_\+\+NORMAL}}
\item 
\#define {\bfseries HAL\+\_\+\+SMBUS\+\_\+\+Slave\+\_\+\+Listen\+\_\+\+IT}~HAL\+\_\+\+SMBUS\+\_\+\+Enable\+Listen\+\_\+\+IT
\item 
\#define {\bfseries HAL\+\_\+\+SMBUS\+\_\+\+Slave\+Addr\+Callback}~HAL\+\_\+\+SMBUS\+\_\+\+Addr\+Callback
\item 
\#define {\bfseries HAL\+\_\+\+SMBUS\+\_\+\+Slave\+Listen\+Cplt\+Callback}~HAL\+\_\+\+SMBUS\+\_\+\+Listen\+Cplt\+Callback
\item 
\#define {\bfseries HAL\+\_\+\+SPI\+\_\+\+Flush\+Rx\+Fifo}~HAL\+\_\+\+SPIEx\+\_\+\+Flush\+Rx\+Fifo
\item 
\#define {\bfseries HAL\+\_\+\+TIM\+\_\+\+DMADelay\+Pulse\+Cplt}~TIM\+\_\+\+DMADelay\+Pulse\+Cplt
\item 
\#define {\bfseries HAL\+\_\+\+TIM\+\_\+\+DMAError}~TIM\+\_\+\+DMAError
\item 
\#define {\bfseries HAL\+\_\+\+TIM\+\_\+\+DMACapture\+Cplt}~TIM\+\_\+\+DMACapture\+Cplt
\item 
\#define {\bfseries HAL\+\_\+\+TIMEx\+\_\+\+DMACommutation\+Cplt}~TIMEx\+\_\+\+DMACommutation\+Cplt
\item 
\#define {\bfseries HAL\+\_\+\+UART\+\_\+\+Wakeup\+Callback}~HAL\+\_\+\+UARTEx\+\_\+\+Wakeup\+Callback
\item 
\#define {\bfseries HAL\+\_\+\+LTDC\+\_\+\+Line\+Even\+Callback}~HAL\+\_\+\+LTDC\+\_\+\+Line\+Event\+Callback
\item 
\#define {\bfseries HAL\+\_\+\+LTDC\+\_\+\+Relaod}~HAL\+\_\+\+LTDC\+\_\+\+Reload
\item 
\#define {\bfseries HAL\+\_\+\+LTDC\+\_\+\+Struct\+Init\+From\+Video\+Config}~HAL\+\_\+\+LTDCEx\+\_\+\+Struct\+Init\+From\+Video\+Config
\item 
\#define {\bfseries HAL\+\_\+\+LTDC\+\_\+\+Struct\+Init\+From\+Adapted\+Command\+Config}~HAL\+\_\+\+LTDCEx\+\_\+\+Struct\+Init\+From\+Adapted\+Command\+Config
\item 
\#define {\bfseries AES\+\_\+\+IT\+\_\+\+CC}~CRYP\+\_\+\+IT\+\_\+\+CC
\item 
\#define {\bfseries AES\+\_\+\+IT\+\_\+\+ERR}~CRYP\+\_\+\+IT\+\_\+\+ERR
\item 
\#define {\bfseries AES\+\_\+\+FLAG\+\_\+\+CCF}~CRYP\+\_\+\+FLAG\+\_\+\+CCF
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+GET\+\_\+\+BOOT\+\_\+\+MODE}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+GET\+\_\+\+BOOT\+\_\+\+MODE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+REMAPMEMORY\+\_\+\+FLASH}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+REMAPMEMORY\+\_\+\+FLASH
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+REMAPMEMORY\+\_\+\+SYSTEMFLASH}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+REMAPMEMORY\+\_\+\+SYSTEMFLASH
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+REMAPMEMORY\+\_\+\+SRAM}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+REMAPMEMORY\+\_\+\+SRAM
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+REMAPMEMORY\+\_\+\+FMC}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+REMAPMEMORY\+\_\+\+FMC
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+REMAPMEMORY\+\_\+\+FMC\+\_\+\+SDRAM}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+REMAPMEMORY\+\_\+\+FMC\+\_\+\+SDRAM
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+REMAPMEMORY\+\_\+\+FSMC}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+REMAPMEMORY\+\_\+\+FSMC
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+REMAPMEMORY\+\_\+\+QUADSPI}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+REMAPMEMORY\+\_\+\+QUADSPI
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FMC\+\_\+\+BANK}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+FMC\+\_\+\+BANK
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+GET\+\_\+\+FLAG}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+GET\+\_\+\+FLAG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+CLEAR\+\_\+\+FLAG}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+CLEAR\+\_\+\+FLAG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+VREFINT\+\_\+\+OUT\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+VREFINT\+\_\+\+OUT\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+VREFINT\+\_\+\+OUT\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+VREFINT\+\_\+\+OUT\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+SRAM2\+\_\+\+WRP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+SYSCFG\+\_\+\+SRAM2\+\_\+\+WRP\+\_\+0\+\_\+31\+\_\+\+ENABLE
\item 
\#define {\bfseries SYSCFG\+\_\+\+FLAG\+\_\+\+VREF\+\_\+\+READY}~SYSCFG\+\_\+\+FLAG\+\_\+\+VREFINT\+\_\+\+READY
\item 
\#define {\bfseries SYSCFG\+\_\+\+FLAG\+\_\+\+RC48}~RCC\+\_\+\+FLAG\+\_\+\+HSI48
\item 
\#define {\bfseries IS\+\_\+\+SYSCFG\+\_\+\+FASTMODEPLUS\+\_\+\+CONFIG}~IS\+\_\+\+I2\+C\+\_\+\+FASTMODEPLUS
\item 
\#define {\bfseries UFB\+\_\+\+MODE\+\_\+\+Bit\+Number}~UFB\+\_\+\+MODE\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries CMP\+\_\+\+PD\+\_\+\+Bit\+Number}~CMP\+\_\+\+PD\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+ENABLING\+\_\+\+CONDITIONS}~ADC\+\_\+\+ENABLING\+\_\+\+CONDITIONS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+DISABLING\+\_\+\+CONDITIONS}~ADC\+\_\+\+DISABLING\+\_\+\+CONDITIONS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+IS\+\_\+\+ENABLED}~ADC\+\_\+\+IS\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC\+\_\+\+IS\+\_\+\+ENABLED}~ADC\+\_\+\+IS\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+IS\+\_\+\+SOFTWARE\+\_\+\+START\+\_\+\+REGULAR}~ADC\+\_\+\+IS\+\_\+\+SOFTWARE\+\_\+\+START\+\_\+\+REGULAR
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+IS\+\_\+\+SOFTWARE\+\_\+\+START\+\_\+\+INJECTED}~ADC\+\_\+\+IS\+\_\+\+SOFTWARE\+\_\+\+START\+\_\+\+INJECTED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+IS\+\_\+\+CONVERSION\+\_\+\+ONGOING\+\_\+\+REGULAR\+\_\+\+INJECTED}~ADC\+\_\+\+IS\+\_\+\+CONVERSION\+\_\+\+ONGOING\+\_\+\+REGULAR\+\_\+\+INJECTED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+IS\+\_\+\+CONVERSION\+\_\+\+ONGOING\+\_\+\+REGULAR}~ADC\+\_\+\+IS\+\_\+\+CONVERSION\+\_\+\+ONGOING\+\_\+\+REGULAR
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+IS\+\_\+\+CONVERSION\+\_\+\+ONGOING\+\_\+\+INJECTED}~ADC\+\_\+\+IS\+\_\+\+CONVERSION\+\_\+\+ONGOING\+\_\+\+INJECTED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+IS\+\_\+\+CONVERSION\+\_\+\+ONGOING}~ADC\+\_\+\+IS\+\_\+\+CONVERSION\+\_\+\+ONGOING
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CLEAR\+\_\+\+ERRORCODE}~ADC\+\_\+\+CLEAR\+\_\+\+ERRORCODE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+GET\+\_\+\+RESOLUTION}~ADC\+\_\+\+GET\+\_\+\+RESOLUTION
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+JSQR\+\_\+\+RK}~ADC\+\_\+\+JSQR\+\_\+\+RK
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+AWD1\+CH}~ADC\+\_\+\+CFGR\+\_\+\+AWD1\+CH\+\_\+\+SHIFT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+AWD23\+CR}~ADC\+\_\+\+CFGR\+\_\+\+AWD23\+CR
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+INJECT\+\_\+\+AUTO\+\_\+\+CONVERSION}~ADC\+\_\+\+CFGR\+\_\+\+INJECT\+\_\+\+AUTO\+\_\+\+CONVERSION
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+INJECT\+\_\+\+CONTEXT\+\_\+\+QUEUE}~ADC\+\_\+\+CFGR\+\_\+\+INJECT\+\_\+\+CONTEXT\+\_\+\+QUEUE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+INJECT\+\_\+\+DISCCONTINUOUS}~ADC\+\_\+\+CFGR\+\_\+\+INJECT\+\_\+\+DISCCONTINUOUS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+REG\+\_\+\+DISCCONTINUOUS}~ADC\+\_\+\+CFGR\+\_\+\+REG\+\_\+\+DISCCONTINUOUS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+DISCONTINUOUS\+\_\+\+NUM}~ADC\+\_\+\+CFGR\+\_\+\+DISCONTINUOUS\+\_\+\+NUM
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+AUTOWAIT}~ADC\+\_\+\+CFGR\+\_\+\+AUTOWAIT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+CONTINUOUS}~ADC\+\_\+\+CFGR\+\_\+\+CONTINUOUS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+OVERRUN}~ADC\+\_\+\+CFGR\+\_\+\+OVERRUN
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+DMACONTREQ}~ADC\+\_\+\+CFGR\+\_\+\+DMACONTREQ
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR\+\_\+\+EXTSEL}~ADC\+\_\+\+CFGR\+\_\+\+EXTSEL\+\_\+\+SET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+JSQR\+\_\+\+JEXTSEL}~ADC\+\_\+\+JSQR\+\_\+\+JEXTSEL\+\_\+\+SET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+OFR\+\_\+\+CHANNEL}~ADC\+\_\+\+OFR\+\_\+\+CHANNEL
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+DIFSEL\+\_\+\+CHANNEL}~ADC\+\_\+\+DIFSEL\+\_\+\+CHANNEL
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CALFACT\+\_\+\+DIFF\+\_\+\+SET}~ADC\+\_\+\+CALFACT\+\_\+\+DIFF\+\_\+\+SET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CALFACT\+\_\+\+DIFF\+\_\+\+GET}~ADC\+\_\+\+CALFACT\+\_\+\+DIFF\+\_\+\+GET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+TRX\+\_\+\+HIGHTHRESHOLD}~ADC\+\_\+\+TRX\+\_\+\+HIGHTHRESHOLD
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+OFFSET\+\_\+\+SHIFT\+\_\+\+RESOLUTION}~ADC\+\_\+\+OFFSET\+\_\+\+SHIFT\+\_\+\+RESOLUTION
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+AWD1\+THRESHOLD\+\_\+\+SHIFT\+\_\+\+RESOLUTION}~ADC\+\_\+\+AWD1\+THRESHOLD\+\_\+\+SHIFT\+\_\+\+RESOLUTION
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+AWD23\+THRESHOLD\+\_\+\+SHIFT\+\_\+\+RESOLUTION}~ADC\+\_\+\+AWD23\+THRESHOLD\+\_\+\+SHIFT\+\_\+\+RESOLUTION
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+COMMON\+\_\+\+REGISTER}~ADC\+\_\+\+COMMON\+\_\+\+REGISTER
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+COMMON\+\_\+\+CCR\+\_\+\+MULTI}~ADC\+\_\+\+COMMON\+\_\+\+CCR\+\_\+\+MULTI
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+MULTIMODE\+\_\+\+IS\+\_\+\+ENABLED}~ADC\+\_\+\+MULTIMODE\+\_\+\+IS\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC\+\_\+\+MULTIMODE\+\_\+\+IS\+\_\+\+ENABLED}~ADC\+\_\+\+MULTIMODE\+\_\+\+IS\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+NONMULTIMODE\+\_\+\+OR\+\_\+\+MULTIMODEMASTER}~ADC\+\_\+\+NONMULTIMODE\+\_\+\+OR\+\_\+\+MULTIMODEMASTER
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+COMMON\+\_\+\+ADC\+\_\+\+OTHER}~ADC\+\_\+\+COMMON\+\_\+\+ADC\+\_\+\+OTHER
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+MULTI\+\_\+\+SLAVE}~ADC\+\_\+\+MULTI\+\_\+\+SLAVE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+SQR1\+\_\+L}~ADC\+\_\+\+SQR1\+\_\+\+L\+\_\+\+SHIFT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+JSQR\+\_\+\+JL}~ADC\+\_\+\+JSQR\+\_\+\+JL\+\_\+\+SHIFT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+JSQR\+\_\+\+RK\+\_\+\+JL}~ADC\+\_\+\+JSQR\+\_\+\+RK\+\_\+\+JL
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CR1\+\_\+\+DISCONTINUOUS\+\_\+\+NUM}~ADC\+\_\+\+CR1\+\_\+\+DISCONTINUOUS\+\_\+\+NUM
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CR1\+\_\+\+SCAN}~ADC\+\_\+\+CR1\+\_\+\+SCAN\+\_\+\+SET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CONVCYCLES\+\_\+\+MAX\+\_\+\+RANGE}~ADC\+\_\+\+CONVCYCLES\+\_\+\+MAX\+\_\+\+RANGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CLOCK\+\_\+\+PRESCALER\+\_\+\+RANGE}~ADC\+\_\+\+CLOCK\+\_\+\+PRESCALER\+\_\+\+RANGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+GET\+\_\+\+CLOCK\+\_\+\+PRESCALER}~ADC\+\_\+\+GET\+\_\+\+CLOCK\+\_\+\+PRESCALER
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+SQR1}~ADC\+\_\+\+SQR1
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+SMPR1}~ADC\+\_\+\+SMPR1
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+SMPR2}~ADC\+\_\+\+SMPR2
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+SQR3\+\_\+\+RK}~ADC\+\_\+\+SQR3\+\_\+\+RK
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+SQR2\+\_\+\+RK}~ADC\+\_\+\+SQR2\+\_\+\+RK
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+SQR1\+\_\+\+RK}~ADC\+\_\+\+SQR1\+\_\+\+RK
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CR2\+\_\+\+CONTINUOUS}~ADC\+\_\+\+CR2\+\_\+\+CONTINUOUS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CR1\+\_\+\+DISCONTINUOUS}~ADC\+\_\+\+CR1\+\_\+\+DISCONTINUOUS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CR1\+\_\+\+SCANCONV}~ADC\+\_\+\+CR1\+\_\+\+SCANCONV
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CR2\+\_\+\+EOCSelection}~ADC\+\_\+\+CR2\+\_\+\+EOCSelection
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CR2\+\_\+\+DMACont\+Req}~ADC\+\_\+\+CR2\+\_\+\+DMACont\+Req
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+JSQR}~ADC\+\_\+\+JSQR
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CHSELR\+\_\+\+CHANNEL}~ADC\+\_\+\+CHSELR\+\_\+\+CHANNEL
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR1\+\_\+\+REG\+\_\+\+DISCCONTINUOUS}~ADC\+\_\+\+CFGR1\+\_\+\+REG\+\_\+\+DISCCONTINUOUS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR1\+\_\+\+AUTOOFF}~ADC\+\_\+\+CFGR1\+\_\+\+AUTOOFF
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR1\+\_\+\+AUTOWAIT}~ADC\+\_\+\+CFGR1\+\_\+\+AUTOWAIT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR1\+\_\+\+CONTINUOUS}~ADC\+\_\+\+CFGR1\+\_\+\+CONTINUOUS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR1\+\_\+\+OVERRUN}~ADC\+\_\+\+CFGR1\+\_\+\+OVERRUN
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR1\+\_\+\+SCANDIR}~ADC\+\_\+\+CFGR1\+\_\+\+SCANDIR
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ADC\+\_\+\+CFGR1\+\_\+\+DMACONTREQ}~ADC\+\_\+\+CFGR1\+\_\+\+DMACONTREQ
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+DHR12\+R1\+\_\+\+ALIGNEMENT}~DAC\+\_\+\+DHR12\+R1\+\_\+\+ALIGNMENT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+DHR12\+R2\+\_\+\+ALIGNEMENT}~DAC\+\_\+\+DHR12\+R2\+\_\+\+ALIGNMENT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+DHR12\+RD\+\_\+\+ALIGNEMENT}~DAC\+\_\+\+DHR12\+RD\+\_\+\+ALIGNMENT
\item 
\#define {\bfseries IS\+\_\+\+DAC\+\_\+\+GENERATE\+\_\+\+WAVE}~IS\+\_\+\+DAC\+\_\+\+WAVE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM1\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM1
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM1\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM1
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM2\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM2
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM2\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM2
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM3\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM3
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM3\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM3
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM4\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM4
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM4\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM4
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM5\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM5
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM5\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM5
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM6\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM6
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM6\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM6
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM7\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM7
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM7\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM7
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM8\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM8
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM8\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM8
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM9\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM9
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM9\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM9
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM10\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM10
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM10\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM10
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM11\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM11
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM11\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM11
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM12\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM12
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM12\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM12
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM13\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM13
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM13\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM13
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM14\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM14
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM14\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM14
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+CAN2\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+CAN2
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+CAN2\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+CAN2
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM15\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM15
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM15\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM15
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM16\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM16
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM16\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM16
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+TIM17\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+TIM17
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+TIM17\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+TIM17
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+RTC\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+RTC
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+RTC\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+RTC
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+WWDG\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+WWDG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+WWDG\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+WWDG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+IWDG\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+IWDG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+IWDG\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+IWDG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+I2\+C1\+\_\+\+TIMEOUT\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+I2\+C1\+\_\+\+TIMEOUT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+I2\+C1\+\_\+\+TIMEOUT\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+I2\+C1\+\_\+\+TIMEOUT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+I2\+C2\+\_\+\+TIMEOUT\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+I2\+C2\+\_\+\+TIMEOUT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+I2\+C2\+\_\+\+TIMEOUT\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+I2\+C2\+\_\+\+TIMEOUT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+I2\+C3\+\_\+\+TIMEOUT\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+I2\+C3\+\_\+\+TIMEOUT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+I2\+C3\+\_\+\+TIMEOUT\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+I2\+C3\+\_\+\+TIMEOUT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+CAN1\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+CAN1
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+CAN1\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+CAN1
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+LPTIM1\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+LPTIM1
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+LPTIM1\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+LPTIM1
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+FREEZE\+\_\+\+LPTIM2\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+FREEZE\+\_\+\+LPTIM2
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UNFREEZE\+\_\+\+LPTIM2\+\_\+\+DBGMCU}~\+\_\+\+\_\+\+HAL\+\_\+\+DBGMCU\+\_\+\+UNFREEZE\+\_\+\+LPTIM2
\item 
\#define \mbox{\hyperlink{group___h_a_l___c_o_m_p___aliased___macros_ga3b6842cbf1a844d87f0ebb50b5322ae9}{\+\_\+\+\_\+\+HAL\+\_\+\+COMP\+\_\+\+EXTI\+\_\+\+RISING\+\_\+\+IT\+\_\+\+ENABLE}}(\+\_\+\+\_\+\+EXTILINE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___h_a_l___c_o_m_p___aliased___macros_ga234c3825b14ee41458a8a58430a1f448}{\+\_\+\+\_\+\+HAL\+\_\+\+COMP\+\_\+\+EXTI\+\_\+\+RISING\+\_\+\+IT\+\_\+\+DISABLE}}(\+\_\+\+\_\+\+EXTILINE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___h_a_l___c_o_m_p___aliased___macros_ga1803e81c3920a4c18f752124e15ee6f7}{\+\_\+\+\_\+\+HAL\+\_\+\+COMP\+\_\+\+EXTI\+\_\+\+FALLING\+\_\+\+IT\+\_\+\+ENABLE}}(\+\_\+\+\_\+\+EXTILINE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___h_a_l___c_o_m_p___aliased___macros_ga28220cc53eb0155d2f6d3197a464092b}{\+\_\+\+\_\+\+HAL\+\_\+\+COMP\+\_\+\+EXTI\+\_\+\+FALLING\+\_\+\+IT\+\_\+\+DISABLE}}(\+\_\+\+\_\+\+EXTILINE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___h_a_l___c_o_m_p___aliased___macros_ga582415dabdca3b746b4713f686b6ddf0}{\+\_\+\+\_\+\+HAL\+\_\+\+COMP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+EXTILINE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___h_a_l___c_o_m_p___aliased___macros_ga50d9fdcb3ccb16b52d567bb3a5821d61}{\+\_\+\+\_\+\+HAL\+\_\+\+COMP\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+EXTILINE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___h_a_l___c_o_m_p___aliased___macros_ga9e0b5c7e3923a1eb153917165210db1a}{\+\_\+\+\_\+\+HAL\+\_\+\+COMP\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___h_a_l___c_o_m_p___aliased___macros_gaffc3545b10b38016b1d695e6f6aab1f7}{\+\_\+\+\_\+\+HAL\+\_\+\+COMP\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG}}(\+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+COMP\+\_\+\+GET\+\_\+\+EXTI\+\_\+\+LINE}~COMP\+\_\+\+GET\+\_\+\+EXTI\+\_\+\+LINE
\item 
\#define \mbox{\hyperlink{group___h_a_l___d_a_c___aliased___macros_ga45c25065fb713820f6dbae0009376e1c}{IS\+\_\+\+DAC\+\_\+\+WAVE}}(WAVE)
\item 
\#define {\bfseries IS\+\_\+\+WRPAREA}~IS\+\_\+\+OB\+\_\+\+WRPAREA
\item 
\#define {\bfseries IS\+\_\+\+TYPEPROGRAM}~IS\+\_\+\+FLASH\+\_\+\+TYPEPROGRAM
\item 
\#define {\bfseries IS\+\_\+\+TYPEPROGRAMFLASH}~IS\+\_\+\+FLASH\+\_\+\+TYPEPROGRAM
\item 
\#define {\bfseries IS\+\_\+\+TYPEERASE}~IS\+\_\+\+FLASH\+\_\+\+TYPEERASE
\item 
\#define {\bfseries IS\+\_\+\+NBSECTORS}~IS\+\_\+\+FLASH\+\_\+\+NBSECTORS
\item 
\#define {\bfseries IS\+\_\+\+OB\+\_\+\+WDG\+\_\+\+SOURCE}~IS\+\_\+\+OB\+\_\+\+IWDG\+\_\+\+SOURCE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+RESET\+\_\+\+CR2}~I2\+C\+\_\+\+RESET\+\_\+\+CR2
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+GENERATE\+\_\+\+START}~I2\+C\+\_\+\+GENERATE\+\_\+\+START
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+FREQ\+\_\+\+RANGE}~I2\+C\+\_\+\+FREQ\+\_\+\+RANGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+RISE\+\_\+\+TIME}~I2\+C\+\_\+\+RISE\+\_\+\+TIME
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+SPEED\+\_\+\+STANDARD}~I2\+C\+\_\+\+SPEED\+\_\+\+STANDARD
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+SPEED\+\_\+\+FAST}~I2\+C\+\_\+\+SPEED\+\_\+\+FAST
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+SPEED}~I2\+C\+\_\+\+SPEED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+7\+BIT\+\_\+\+ADD\+\_\+\+WRITE}~I2\+C\+\_\+7\+BIT\+\_\+\+ADD\+\_\+\+WRITE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+7\+BIT\+\_\+\+ADD\+\_\+\+READ}~I2\+C\+\_\+7\+BIT\+\_\+\+ADD\+\_\+\+READ
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+10\+BIT\+\_\+\+ADDRESS}~I2\+C\+\_\+10\+BIT\+\_\+\+ADDRESS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+10\+BIT\+\_\+\+HEADER\+\_\+\+WRITE}~I2\+C\+\_\+10\+BIT\+\_\+\+HEADER\+\_\+\+WRITE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+10\+BIT\+\_\+\+HEADER\+\_\+\+READ}~I2\+C\+\_\+10\+BIT\+\_\+\+HEADER\+\_\+\+READ
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+MEM\+\_\+\+ADD\+\_\+\+MSB}~I2\+C\+\_\+\+MEM\+\_\+\+ADD\+\_\+\+MSB
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+MEM\+\_\+\+ADD\+\_\+\+LSB}~I2\+C\+\_\+\+MEM\+\_\+\+ADD\+\_\+\+LSB
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+I2\+C\+\_\+\+FREQRANGE}~I2\+C\+\_\+\+FREQRANGE
\item 
\#define {\bfseries IS\+\_\+\+I2\+S\+\_\+\+INSTANCE}~IS\+\_\+\+I2\+S\+\_\+\+ALL\+\_\+\+INSTANCE
\item 
\#define {\bfseries IS\+\_\+\+I2\+S\+\_\+\+INSTANCE\+\_\+\+EXT}~IS\+\_\+\+I2\+S\+\_\+\+ALL\+\_\+\+INSTANCE\+\_\+\+EXT
\item 
\#define {\bfseries \+\_\+\+\_\+\+IRDA\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+IRDA\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+IRDA\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+IRDA\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+IRDA\+\_\+\+GETCLOCKSOURCE}~IRDA\+\_\+\+GETCLOCKSOURCE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+IRDA\+\_\+\+MASK\+\_\+\+COMPUTATION}~IRDA\+\_\+\+MASK\+\_\+\+COMPUTATION
\item 
\#define {\bfseries \+\_\+\+\_\+\+IRDA\+\_\+\+GETCLOCKSOURCE}~IRDA\+\_\+\+GETCLOCKSOURCE
\item 
\#define {\bfseries \+\_\+\+\_\+\+IRDA\+\_\+\+MASK\+\_\+\+COMPUTATION}~IRDA\+\_\+\+MASK\+\_\+\+COMPUTATION
\item 
\#define {\bfseries IS\+\_\+\+IRDA\+\_\+\+ONEBIT\+\_\+\+SAMPLE}~IS\+\_\+\+IRDA\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+IWDG\+\_\+\+ENABLE\+\_\+\+WRITE\+\_\+\+ACCESS}~IWDG\+\_\+\+ENABLE\+\_\+\+WRITE\+\_\+\+ACCESS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+IWDG\+\_\+\+DISABLE\+\_\+\+WRITE\+\_\+\+ACCESS}~IWDG\+\_\+\+DISABLE\+\_\+\+WRITE\+\_\+\+ACCESS
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+LPTIM\+\_\+\+ENABLE\+\_\+\+INTERRUPT}~\+\_\+\+\_\+\+HAL\+\_\+\+LPTIM\+\_\+\+ENABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+LPTIM\+\_\+\+DISABLE\+\_\+\+INTERRUPT}~\+\_\+\+\_\+\+HAL\+\_\+\+LPTIM\+\_\+\+DISABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+LPTIM\+\_\+\+GET\+\_\+\+ITSTATUS}~\+\_\+\+\_\+\+HAL\+\_\+\+LPTIM\+\_\+\+GET\+\_\+\+IT\+\_\+\+SOURCE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CSR\+\_\+\+OPAXPD}~OPAMP\+\_\+\+CSR\+\_\+\+OPAXPD
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CSR\+\_\+\+S3\+SELX}~OPAMP\+\_\+\+CSR\+\_\+\+S3\+SELX
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CSR\+\_\+\+S4\+SELX}~OPAMP\+\_\+\+CSR\+\_\+\+S4\+SELX
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CSR\+\_\+\+S5\+SELX}~OPAMP\+\_\+\+CSR\+\_\+\+S5\+SELX
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CSR\+\_\+\+S6\+SELX}~OPAMP\+\_\+\+CSR\+\_\+\+S6\+SELX
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CSR\+\_\+\+OPAXCAL\+\_\+L}~OPAMP\+\_\+\+CSR\+\_\+\+OPAXCAL\+\_\+L
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CSR\+\_\+\+OPAXCAL\+\_\+H}~OPAMP\+\_\+\+CSR\+\_\+\+OPAXCAL\+\_\+H
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CSR\+\_\+\+OPAXLPM}~OPAMP\+\_\+\+CSR\+\_\+\+OPAXLPM
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CSR\+\_\+\+ALL\+\_\+\+SWITCHES}~OPAMP\+\_\+\+CSR\+\_\+\+ALL\+\_\+\+SWITCHES
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CSR\+\_\+\+ANAWSELX}~OPAMP\+\_\+\+CSR\+\_\+\+ANAWSELX
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CSR\+\_\+\+OPAXCALOUT}~OPAMP\+\_\+\+CSR\+\_\+\+OPAXCALOUT
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+OFFSET\+\_\+\+TRIM\+\_\+\+BITSPOSITION}~OPAMP\+\_\+\+OFFSET\+\_\+\+TRIM\+\_\+\+BITSPOSITION
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+OFFSET\+\_\+\+TRIM\+\_\+\+SET}~OPAMP\+\_\+\+OFFSET\+\_\+\+TRIM\+\_\+\+SET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVD\+\_\+\+EVENT\+\_\+\+DISABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga8bd379e960497722450c7cea474a7e7a}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+EVENT}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVD\+\_\+\+EVENT\+\_\+\+ENABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_gae5ba5672fe8cb7c1686c7f2cc211b128}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+EVENT}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+FALLINGTRIGGER\+\_\+\+DISABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga1ca57168205f8cd8d1014e6eb9465f2d}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+FALLING\+\_\+\+EDGE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+FALLINGTRIGGER\+\_\+\+ENABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga5b971478563a00e1ee1a9d8ca8054e08}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+RISINGTRIGGER\+\_\+\+DISABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga1ca8fd7f3286a176f6be540c75a004c6}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+EDGE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+RISINGTRIGGER\+\_\+\+ENABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga7bef3f30c9fe267c99d5240fbf3f878c}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVM\+\_\+\+EVENT\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVM\+\_\+\+EVENT\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVM\+\_\+\+EVENT\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVM\+\_\+\+EVENT\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVM\+\_\+\+EXTI\+\_\+\+FALLINGTRIGGER\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVM\+\_\+\+EXTI\+\_\+\+FALLINGTRIGGER\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVM\+\_\+\+EXTI\+\_\+\+FALLINGTRIGGER\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVM\+\_\+\+EXTI\+\_\+\+FALLINGTRIGGER\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVM\+\_\+\+EXTI\+\_\+\+RISINGTRIGGER\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVM\+\_\+\+EXTI\+\_\+\+RISINGTRIGGER\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVM\+\_\+\+EXTI\+\_\+\+RISINGTRIGGER\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVM\+\_\+\+EXTI\+\_\+\+RISINGTRIGGER\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+INTERNALWAKEUP\+\_\+\+DISABLE}~HAL\+\_\+\+PWREx\+\_\+\+Disable\+Internal\+Wake\+Up\+Line
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+INTERNALWAKEUP\+\_\+\+ENABLE}~HAL\+\_\+\+PWREx\+\_\+\+Enable\+Internal\+Wake\+Up\+Line
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PULL\+\_\+\+UP\+\_\+\+DOWN\+\_\+\+CONFIG\+\_\+\+DISABLE}~HAL\+\_\+\+PWREx\+\_\+\+Disable\+Pull\+Up\+Pull\+Down\+Config
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PULL\+\_\+\+UP\+\_\+\+DOWN\+\_\+\+CONFIG\+\_\+\+ENABLE}~HAL\+\_\+\+PWREx\+\_\+\+Enable\+Pull\+Up\+Pull\+Down\+Config
\item 
\#define \mbox{\hyperlink{group___h_a_l___p_w_r___aliased___macros_ga288b776e260c65b683ae05a335f5826b}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+EGDE\+\_\+\+TRIGGER}}()
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+EVENT\+\_\+\+DISABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga8bd379e960497722450c7cea474a7e7a}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+EVENT}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+EVENT\+\_\+\+ENABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_gae5ba5672fe8cb7c1686c7f2cc211b128}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+EVENT}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+FALLINGTRIGGER\+\_\+\+DISABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga1ca57168205f8cd8d1014e6eb9465f2d}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+FALLING\+\_\+\+EDGE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+FALLINGTRIGGER\+\_\+\+ENABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga5b971478563a00e1ee1a9d8ca8054e08}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+RISINGTRIGGER\+\_\+\+DISABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga1ca8fd7f3286a176f6be540c75a004c6}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+RISING\+\_\+\+EDGE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+RISINGTRIGGER\+\_\+\+ENABLE}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga7bef3f30c9fe267c99d5240fbf3f878c}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+FALLING\+\_\+\+EGDE\+\_\+\+TRIGGER}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga5b971478563a00e1ee1a9d8ca8054e08}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+RISING\+\_\+\+EDGE\+\_\+\+TRIGGER}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga7bef3f30c9fe267c99d5240fbf3f878c}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE}}
\item 
\#define \mbox{\hyperlink{group___h_a_l___p_w_r___aliased___macros_gaec66f2306538bb9002387ceafeb38462}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVM\+\_\+\+DISABLE}}()
\item 
\#define \mbox{\hyperlink{group___h_a_l___p_w_r___aliased___macros_ga48b28ca62d86e12f33848cbb20ea16dc}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVM\+\_\+\+ENABLE}}()
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+SRAM2\+CONTENT\+\_\+\+PRESERVE\+\_\+\+DISABLE}~HAL\+\_\+\+PWREx\+\_\+\+Disable\+SRAM2\+Content\+Retention
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+SRAM2\+CONTENT\+\_\+\+PRESERVE\+\_\+\+ENABLE}~HAL\+\_\+\+PWREx\+\_\+\+Enable\+SRAM2\+Content\+Retention
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VDDIO2\+\_\+\+DISABLE}~HAL\+\_\+\+PWREx\+\_\+\+Disable\+Vdd\+IO2
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VDDIO2\+\_\+\+ENABLE}~HAL\+\_\+\+PWREx\+\_\+\+Enable\+Vdd\+IO2
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VDDIO2\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+EGDE\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VDDIO2\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VDDIO2\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+FALLING\+\_\+\+EGDE\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VDDIO2\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VDDUSB\+\_\+\+DISABLE}~HAL\+\_\+\+PWREx\+\_\+\+Disable\+Vdd\+USB
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+VDDUSB\+\_\+\+ENABLE}~HAL\+\_\+\+PWREx\+\_\+\+Enable\+Vdd\+USB
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG}~\mbox{\hyperlink{group___p_w_r___exported___macro_gac0fb2218bc050f5d8fdb1a3f28590352}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT}~\mbox{\hyperlink{group___p_w_r___exported___macro_gad240d7bf8f15191b068497b9aead1f1f}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga3180f039cf14ef78a64089f387f8f9c2}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT}~\mbox{\hyperlink{group___p_w_r___exported___macro_gaba4a7968f5c4c4ca6a7047b147ba18d4}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG}~\mbox{\hyperlink{group___p_w_r___exported___macro_ga5e66fa75359b51066e0731ac1e5ae438}{\+\_\+\+\_\+\+HAL\+\_\+\+PWR\+\_\+\+PVD\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG}}
\item 
\#define {\bfseries RCC\+\_\+\+Stop\+Wake\+Up\+Clock\+\_\+\+MSI}~RCC\+\_\+\+STOP\+\_\+\+WAKEUPCLOCK\+\_\+\+MSI
\item 
\#define {\bfseries RCC\+\_\+\+Stop\+Wake\+Up\+Clock\+\_\+\+HSI}~RCC\+\_\+\+STOP\+\_\+\+WAKEUPCLOCK\+\_\+\+HSI
\item 
\#define {\bfseries HAL\+\_\+\+RCC\+\_\+\+CCSCallback}~HAL\+\_\+\+RCC\+\_\+\+CSSCallback
\item 
\#define \mbox{\hyperlink{group___h_a_l___r_c_c___aliased_gac6eb1ec87a15e51601d0957fdf17e870}{HAL\+\_\+\+RC48\+\_\+\+Enable\+Buffer\+\_\+\+Cmd}}(cmd)
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC2\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC2\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC2\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC2\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC2\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC2\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC3\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC3\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC3\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC3\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC3\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC3\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC3\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC3\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+AES\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AES\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+AES\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AES\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+AES\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AES\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+AES\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AES\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+AES\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AES\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+AES\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AES\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRYP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRYP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRYP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRYP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRYP\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRYP\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRYP\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRYP\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRYP\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRYP\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRYP\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRYP\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+AFIO\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AFIO\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+AFIO\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AFIO\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+AFIO\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AFIO\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+AFIO\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AFIO\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+AHB\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+AHB\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+AHB1\+\_\+\+FORCE\+\_\+\+RESET}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga87d828d91e67aaa931853a60779826c2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB1\+\_\+\+FORCE\+\_\+\+RESET}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+AHB1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+AHB2\+\_\+\+FORCE\+\_\+\+RESET}~\mbox{\hyperlink{group___r_c_c___exported___macros_gae82cd541f933be46ec8d6c3ea50d402c}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB2\+\_\+\+FORCE\+\_\+\+RESET}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+AHB2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+AHB3\+\_\+\+FORCE\+\_\+\+RESET}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga230a57ed6c129076b4fd17bdb07d79f6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB3\+\_\+\+FORCE\+\_\+\+RESET}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+AHB3\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+AHB3\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+APB1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+APB1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+APB2\+\_\+\+FORCE\+\_\+\+RESET}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga8788da8c644ad0cc54912baede7d49b4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB2\+\_\+\+FORCE\+\_\+\+RESET}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+APB2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+APB2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+BKP\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKP\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+BKP\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKP\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+BKP\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKP\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+BKP\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKP\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN2\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN2\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN2\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN2\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN2\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN2\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CEC\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CEC\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+COMP\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+COMP\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+COMP\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+COMP\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+COMP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+COMP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+COMP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CEC\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CEC\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRC\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRC\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRC\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRC\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRC\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRC\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRC\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRC\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DBGMCU\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DBGMCU\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DBGMCU\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DBGMCU\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DBGMCU\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DBGMCU\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DBGMCU\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DBGMCU\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DFSDM\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DFSDM\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga49fc2c82ba0753e462ea8eb91c634a98}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga568e4d004285fe009bc4e5d33e13af61}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMAC\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMAC\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMAC\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMAC\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMAC\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMAC\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMAC\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMAC\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACRX\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACRX\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACRX\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACRX\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACTX\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACTX\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACTX\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACTX\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FIREWALL\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FIREWALL\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FIREWALL\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FIREWALL\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLASH\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLASH\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLASH\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLASH\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLASH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLASH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLASH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLASH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLASH\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLASH\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLASH\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLASH\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLITF\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLITF\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLITF\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLITF\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLITF\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLITF\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLITF\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLITF\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLITF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLITF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLITF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLITF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FMC\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+FMC\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+FSMC\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FSMC\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FSMC\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FSMC\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga1fde58d775fd2458002df817a68f486e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_gaff8820b47bd3764e7cded76b9368460b}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOA\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOA\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOB\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOB\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOC\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOC\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOD\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOD\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOE\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOE\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOF\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOF\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOG\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOG\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOH\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOH\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C2\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C3\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C3\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+LCD\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LCD\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LCD\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LCD\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LCD\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LCD\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LCD\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LCD\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LCD\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LCD\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+LCD\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LCD\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM2\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPTIM2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPTIM2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPUART1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+LPUART1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LPUART1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+OPAMP\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OPAMP\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGFS\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGFS\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGFS\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGFS\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGFS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGFS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGFS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGFS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGFS\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGFS\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGFS\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGFS\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+PWR\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PWR\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+PWR\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PWR\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+PWR\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PWR\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+PWR\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PWR\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+PWR\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PWR\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+PWR\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PWR\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+QSPI\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+QSPI\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+QSPI\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+QSPI\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+QSPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+QSPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+QSPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+QSPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+QSPI\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+QSPI\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+QSPI\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+QSPI\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+RNG\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+RNG\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+RNG\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI2\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI2\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI2\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI2\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI2\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI2\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SAI2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SAI2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDIO\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDIO\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDIO\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDIO\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDMMC\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDMMC\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDMMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDMMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDMMC\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDMMC\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDMMC\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI2\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI3\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI3\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SRAM\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SRAM\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SRAM\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SRAM\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SRAM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SRAM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SRAM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SRAM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SRAM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SWPMI1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SWPMI1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SWPMI1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_gafc3ffcbb86e4913ae336ba094ca199e1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga6e3a8ca9e554e3aa7aba57d034725655}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+SYSCFG\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SYSCFG\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_gad693d7300ed7134b60bb1a645e762358}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga6ce02f1b2689c664010bebc2363d1db4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM10\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM10\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM10\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM10\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM10\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM10\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM10\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM10\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM11\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM11\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM11\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM11\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM11\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM11\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM11\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM11\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM12\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM12\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM13\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM13\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM14\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM14\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM15\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM15\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM16\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM16\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM17\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM17\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga2e895257faa38376b9cdfcd756909a43}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga975142c90b4e1baf21b361524518235d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM2\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM3\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM3\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM4\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM4\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM5\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM5\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM6\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM6\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM7\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM7\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM8\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM8\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM9\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM9\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM9\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM9\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM9\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM9\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM9\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM9\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TSC\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TSC\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TSC\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TSC\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TSC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TSC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TSC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TSC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TSC\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TSC\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TSC\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TSC\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART4\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART4\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART5\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART5\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART2\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART3\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART3\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART4\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART4\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART4\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART4\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART5\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART5\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART5\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART5\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART7\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART7\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART7\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART7\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART8\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART8\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART8\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART8\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+WWDG\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+WWDG\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+WWDG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+WWDG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+WWDG\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+WWDG\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM21\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM21\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM21\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM21\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM21\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM21\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM21\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM21\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM21\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM21\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM21\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM21\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM22\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM22\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM22\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM22\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM22\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM22\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM22\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM22\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM22\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM22\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM22\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM22\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRS\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRS\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+RCC\+\_\+\+BACKUPRESET\+\_\+\+FORCE}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga3bf7da608ff985873ca8e248fb1dc4f0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BACKUPRESET\+\_\+\+FORCE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+RCC\+\_\+\+BACKUPRESET\+\_\+\+RELEASE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BACKUPRESET\+\_\+\+RELEASE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM9\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM9\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM9\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM9\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM10\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM10\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM10\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM10\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM11\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM11\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM11\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM11\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACPTP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACPTP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACPTP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACPTP\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACPTP\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACPTP\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACPTP\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACPTP\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HASH\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HASH\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HASH\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HASH\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HASH\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HASH\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HASH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HASH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HASH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HASH\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HASH\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HASH\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI5\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI5\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI5\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI6\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI6\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LTDC\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LTDC\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LTDC\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LTDC\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+LTDC\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LTDC\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+LTDC\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LTDC\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+LTDC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+LTDC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMAC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMAC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMAC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMAC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACTX\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACTX\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACTX\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACTX\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACRX\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACRX\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETHMACRX\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETHMACRX\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+BKPSRAM\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPSRAM\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+BKPSRAM\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPSRAM\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+BKPSRAM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPSRAM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+BKPSRAM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+BKPSRAM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CCMDATARAMEN\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CCMDATARAMEN\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CCMDATARAMEN\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CCMDATARAMEN\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART6\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART6\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART6\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI4\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI4\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOI\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOI\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOI\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOI\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOI\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOI\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOI\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOI\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOJ\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOJ\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOJ\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOK\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOK\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETH\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETH\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ETH\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ETH\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_ga16fbc8a6891716f91d96e23fd17c01e2}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DCMI\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DCMI\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\mbox{\hyperlink{group___r_c_c___exported___macros_gaf6fa397bcd717325032e3425fd424988}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DCMI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART7\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART7\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART7\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART8\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART8\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART8\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGHS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGHS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGHS\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGHS\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGHSULPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+OTGHSULPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGHS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGHS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGHS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGHS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGHS\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGHS\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGHSULPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGHSULPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGHSULPI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGHSULPI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+ULPI\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SRAM3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SRAM3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+CAN2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CAN2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC2\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC3\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FSMC\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FSMC\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+FSMC\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FSMC\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+FSMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FSMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+FSMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FSMC\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDIO\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDIO\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDIO\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDIO\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDIO\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDIO\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDIO\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDIO\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+D\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+D\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+D\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGFS\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+OTGFS\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC12\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC12\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC34\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC34\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC34\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC34\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC2\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC2\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC2\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC2\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM18\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM18\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM18\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM18\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM19\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM19\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM19\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM19\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM20\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM20\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM20\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM20\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HRTIM1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HRTIM1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HRTIM1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HRTIM1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC1\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC2\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC2\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC3\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC3\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC1\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC2\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC2\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC3\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC3\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC12\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC12\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC34\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC34\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC34\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC34\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC2\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC2\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM18\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM18\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM18\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM18\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM19\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM19\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM19\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM19\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM20\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM20\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM20\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM20\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HRTIM1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HRTIM1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HRTIM1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HRTIM1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC1\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC2\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC2\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC3\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC3\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC1\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC2\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC2\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC3\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC3\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC34\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC34\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+ADC34\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+ADC34\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+CEC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+CEC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CEC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+CRC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+DAC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DAC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\mbox{\hyperlink{group___r_c_c___exported___macros_gaab05e603c9cadd72e4b6397837b46cef}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+DMA2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DMA2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLITF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLITF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+FLITF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FLITF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+FMC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+FMC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+FMC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\mbox{\hyperlink{group___r_c_c___exported___macros_gad1edbd9407c814110f04c1a609a214e4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOA\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOD\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOD\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOD\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOE\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOE\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOE\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOF\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOH\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+GPIOH\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GPIOH\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HRTIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HRTIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HRTIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+HRTIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+I2\+C3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+C3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+PWR\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PWR\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+PWR\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+PWR\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SYSCFG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\mbox{\hyperlink{group___r_c_c___exported___macros_gad1ea95d1d5f3a2ecf2b903c4ed22e7c6}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+SYSCFG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SYSCFG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SPI4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SPI4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SDADC3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SDADC3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SRAM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SRAM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+SRAM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+SRAM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\mbox{\hyperlink{group___r_c_c___exported___macros_gad2b7c3a381d791c4ee728e303935832a}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\mbox{\hyperlink{group___r_c_c___exported___macros_gadee5016adb1c8b62a5bb05f055859de0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM6\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM7\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM8\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM12\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM13\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM13\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM13\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM14\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM14\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM14\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM15\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM15\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM15\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM16\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM16\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM16\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM17\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM17\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM17\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM18\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM18\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM18\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM18\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM19\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM19\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM19\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM19\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM20\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM20\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TIM20\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TIM20\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TSC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TSC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+TSC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+TSC\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART4\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+UART5\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART2\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USART3\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+USB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+USB\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+WWDG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+WWDG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+WWDG\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+SCLK}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+S\+\_\+\+CONFIG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+SCLK\+\_\+\+CONFIG}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+I2\+S\+\_\+\+CONFIG
\item 
\#define {\bfseries \+\_\+\+\_\+\+RCC\+\_\+\+PLLSRC}~RCC\+\_\+\+GET\+\_\+\+PLL\+\_\+\+OSCSOURCE
\item 
\#define {\bfseries IS\+\_\+\+RCC\+\_\+\+MSIRANGE}~IS\+\_\+\+RCC\+\_\+\+MSI\+\_\+\+CLOCK\+\_\+\+RANGE
\item 
\#define {\bfseries IS\+\_\+\+RCC\+\_\+\+RTCCLK\+\_\+\+SOURCE}~IS\+\_\+\+RCC\+\_\+\+RTCCLKSOURCE
\item 
\#define {\bfseries IS\+\_\+\+RCC\+\_\+\+SYSCLK\+\_\+\+DIV}~IS\+\_\+\+RCC\+\_\+\+HCLK
\item 
\#define {\bfseries IS\+\_\+\+RCC\+\_\+\+HCLK\+\_\+\+DIV}~IS\+\_\+\+RCC\+\_\+\+PCLK
\item 
\#define {\bfseries IS\+\_\+\+RCC\+\_\+\+PERIPHCLK}~IS\+\_\+\+RCC\+\_\+\+PERIPHCLOCK
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+HSI14}~RCC\+\_\+\+IT\+\_\+\+HSI14\+RDY
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+CSSLSE}~RCC\+\_\+\+IT\+\_\+\+LSECSS
\item 
\#define {\bfseries RCC\+\_\+\+IT\+\_\+\+CSSHSE}~RCC\+\_\+\+IT\+\_\+\+CSS
\item 
\#define {\bfseries RCC\+\_\+\+PLLMUL\+\_\+3}~RCC\+\_\+\+PLL\+\_\+\+MUL3
\item 
\#define {\bfseries RCC\+\_\+\+PLLMUL\+\_\+4}~RCC\+\_\+\+PLL\+\_\+\+MUL4
\item 
\#define {\bfseries RCC\+\_\+\+PLLMUL\+\_\+6}~RCC\+\_\+\+PLL\+\_\+\+MUL6
\item 
\#define {\bfseries RCC\+\_\+\+PLLMUL\+\_\+8}~RCC\+\_\+\+PLL\+\_\+\+MUL8
\item 
\#define {\bfseries RCC\+\_\+\+PLLMUL\+\_\+12}~RCC\+\_\+\+PLL\+\_\+\+MUL12
\item 
\#define {\bfseries RCC\+\_\+\+PLLMUL\+\_\+16}~RCC\+\_\+\+PLL\+\_\+\+MUL16
\item 
\#define {\bfseries RCC\+\_\+\+PLLMUL\+\_\+24}~RCC\+\_\+\+PLL\+\_\+\+MUL24
\item 
\#define {\bfseries RCC\+\_\+\+PLLMUL\+\_\+32}~RCC\+\_\+\+PLL\+\_\+\+MUL32
\item 
\#define {\bfseries RCC\+\_\+\+PLLMUL\+\_\+48}~RCC\+\_\+\+PLL\+\_\+\+MUL48
\item 
\#define {\bfseries RCC\+\_\+\+PLLDIV\+\_\+2}~RCC\+\_\+\+PLL\+\_\+\+DIV2
\item 
\#define {\bfseries RCC\+\_\+\+PLLDIV\+\_\+3}~RCC\+\_\+\+PLL\+\_\+\+DIV3
\item 
\#define {\bfseries RCC\+\_\+\+PLLDIV\+\_\+4}~RCC\+\_\+\+PLL\+\_\+\+DIV4
\item 
\#define {\bfseries IS\+\_\+\+RCC\+\_\+\+MCOSOURCE}~IS\+\_\+\+RCC\+\_\+\+MCO1\+SOURCE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MCO\+\_\+\+CONFIG}~\mbox{\hyperlink{group___r_c_c_ex___m_c_ox___clock___config_ga7e5f7f1efc92794b6f0e96068240b45e}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+MCO1\+\_\+\+CONFIG}}
\item 
\#define {\bfseries RCC\+\_\+\+MCO\+\_\+\+NODIV}~RCC\+\_\+\+MCODIV\+\_\+1
\item 
\#define {\bfseries RCC\+\_\+\+MCO\+\_\+\+DIV1}~RCC\+\_\+\+MCODIV\+\_\+1
\item 
\#define {\bfseries RCC\+\_\+\+MCO\+\_\+\+DIV2}~RCC\+\_\+\+MCODIV\+\_\+2
\item 
\#define {\bfseries RCC\+\_\+\+MCO\+\_\+\+DIV4}~RCC\+\_\+\+MCODIV\+\_\+4
\item 
\#define {\bfseries RCC\+\_\+\+MCO\+\_\+\+DIV8}~RCC\+\_\+\+MCODIV\+\_\+8
\item 
\#define {\bfseries RCC\+\_\+\+MCO\+\_\+\+DIV16}~RCC\+\_\+\+MCODIV\+\_\+16
\item 
\#define {\bfseries RCC\+\_\+\+MCO\+\_\+\+DIV32}~RCC\+\_\+\+MCODIV\+\_\+32
\item 
\#define {\bfseries RCC\+\_\+\+MCO\+\_\+\+DIV64}~RCC\+\_\+\+MCODIV\+\_\+64
\item 
\#define {\bfseries RCC\+\_\+\+MCO\+\_\+\+DIV128}~RCC\+\_\+\+MCODIV\+\_\+128
\item 
\#define {\bfseries RCC\+\_\+\+MCOSOURCE\+\_\+\+NONE}~RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+NOCLOCK
\item 
\#define {\bfseries RCC\+\_\+\+MCOSOURCE\+\_\+\+LSI}~RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+LSI
\item 
\#define {\bfseries RCC\+\_\+\+MCOSOURCE\+\_\+\+LSE}~RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+LSE
\item 
\#define {\bfseries RCC\+\_\+\+MCOSOURCE\+\_\+\+SYSCLK}~RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+SYSCLK
\item 
\#define {\bfseries RCC\+\_\+\+MCOSOURCE\+\_\+\+HSI}~RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+HSI
\item 
\#define {\bfseries RCC\+\_\+\+MCOSOURCE\+\_\+\+HSI14}~RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+HSI14
\item 
\#define {\bfseries RCC\+\_\+\+MCOSOURCE\+\_\+\+HSI48}~RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+HSI48
\item 
\#define {\bfseries RCC\+\_\+\+MCOSOURCE\+\_\+\+HSE}~RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+HSE
\item 
\#define {\bfseries RCC\+\_\+\+MCOSOURCE\+\_\+\+PLLCLK\+\_\+\+DIV1}~RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+PLLCLK
\item 
\#define {\bfseries RCC\+\_\+\+MCOSOURCE\+\_\+\+PLLCLK\+\_\+\+NODIV}~RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+PLLCLK
\item 
\#define {\bfseries RCC\+\_\+\+MCOSOURCE\+\_\+\+PLLCLK\+\_\+\+DIV2}~RCC\+\_\+\+MCO1\+SOURCE\+\_\+\+PLLCLK\+\_\+\+DIV2
\item 
\#define {\bfseries RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+NONE}~RCC\+\_\+\+RTCCLKSOURCE\+\_\+\+NO\+\_\+\+CLK
\item 
\#define {\bfseries RCC\+\_\+\+USBCLK\+\_\+\+PLLSAI1}~RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLLSAI1
\item 
\#define {\bfseries RCC\+\_\+\+USBCLK\+\_\+\+PLL}~RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLL
\item 
\#define {\bfseries RCC\+\_\+\+USBCLK\+\_\+\+MSI}~RCC\+\_\+\+USBCLKSOURCE\+\_\+\+MSI
\item 
\#define {\bfseries RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLLCLK}~RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLL
\item 
\#define {\bfseries RCC\+\_\+\+USBPLLCLK\+\_\+\+DIV1}~RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLL
\item 
\#define {\bfseries RCC\+\_\+\+USBPLLCLK\+\_\+\+DIV1\+\_\+5}~RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLL\+\_\+\+DIV1\+\_\+5
\item 
\#define {\bfseries RCC\+\_\+\+USBPLLCLK\+\_\+\+DIV2}~RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLL\+\_\+\+DIV2
\item 
\#define {\bfseries RCC\+\_\+\+USBPLLCLK\+\_\+\+DIV3}~RCC\+\_\+\+USBCLKSOURCE\+\_\+\+PLL\+\_\+\+DIV3
\item 
\#define {\bfseries HSION\+\_\+\+Bit\+Number}~RCC\+\_\+\+HSION\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries HSION\+\_\+\+BITNUMBER}~RCC\+\_\+\+HSION\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries HSEON\+\_\+\+Bit\+Number}~RCC\+\_\+\+HSEON\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries HSEON\+\_\+\+BITNUMBER}~RCC\+\_\+\+HSEON\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries MSION\+\_\+\+BITNUMBER}~RCC\+\_\+\+MSION\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries CSSON\+\_\+\+Bit\+Number}~RCC\+\_\+\+CSSON\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries CSSON\+\_\+\+BITNUMBER}~RCC\+\_\+\+CSSON\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries PLLON\+\_\+\+Bit\+Number}~RCC\+\_\+\+PLLON\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries PLLON\+\_\+\+BITNUMBER}~RCC\+\_\+\+PLLON\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries PLLI2\+SON\+\_\+\+Bit\+Number}~RCC\+\_\+\+PLLI2\+SON\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries I2\+SSRC\+\_\+\+Bit\+Number}~RCC\+\_\+\+I2\+SSRC\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries RTCEN\+\_\+\+Bit\+Number}~RCC\+\_\+\+RTCEN\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries RTCEN\+\_\+\+BITNUMBER}~RCC\+\_\+\+RTCEN\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries BDRST\+\_\+\+Bit\+Number}~RCC\+\_\+\+BDRST\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries BDRST\+\_\+\+BITNUMBER}~RCC\+\_\+\+BDRST\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries RTCRST\+\_\+\+BITNUMBER}~RCC\+\_\+\+RTCRST\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries LSION\+\_\+\+Bit\+Number}~RCC\+\_\+\+LSION\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries LSION\+\_\+\+BITNUMBER}~RCC\+\_\+\+LSION\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries LSEON\+\_\+\+Bit\+Number}~RCC\+\_\+\+LSEON\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries LSEON\+\_\+\+BITNUMBER}~RCC\+\_\+\+LSEON\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries LSEBYP\+\_\+\+BITNUMBER}~RCC\+\_\+\+LSEBYP\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries PLLSAION\+\_\+\+Bit\+Number}~RCC\+\_\+\+PLLSAION\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries TIMPRE\+\_\+\+Bit\+Number}~RCC\+\_\+\+TIMPRE\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries RMVF\+\_\+\+Bit\+Number}~RCC\+\_\+\+RMVF\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries RMVF\+\_\+\+BITNUMBER}~RCC\+\_\+\+RMVF\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries RCC\+\_\+\+CR2\+\_\+\+HSI14\+TRIM\+\_\+\+Bit\+Number}~RCC\+\_\+\+HSI14\+TRIM\+\_\+\+BIT\+\_\+\+NUMBER
\item 
\#define {\bfseries CR\+\_\+\+BYTE2\+\_\+\+ADDRESS}~RCC\+\_\+\+CR\+\_\+\+BYTE2\+\_\+\+ADDRESS
\item 
\#define {\bfseries CIR\+\_\+\+BYTE1\+\_\+\+ADDRESS}~RCC\+\_\+\+CIR\+\_\+\+BYTE1\+\_\+\+ADDRESS
\item 
\#define {\bfseries CIR\+\_\+\+BYTE2\+\_\+\+ADDRESS}~RCC\+\_\+\+CIR\+\_\+\+BYTE2\+\_\+\+ADDRESS
\item 
\#define {\bfseries BDCR\+\_\+\+BYTE0\+\_\+\+ADDRESS}~RCC\+\_\+\+BDCR\+\_\+\+BYTE0\+\_\+\+ADDRESS
\item 
\#define {\bfseries DBP\+\_\+\+TIMEOUT\+\_\+\+VALUE}~RCC\+\_\+\+DBP\+\_\+\+TIMEOUT\+\_\+\+VALUE
\item 
\#define {\bfseries LSE\+\_\+\+TIMEOUT\+\_\+\+VALUE}~RCC\+\_\+\+LSE\+\_\+\+TIMEOUT\+\_\+\+VALUE
\item 
\#define {\bfseries CR\+\_\+\+HSION\+\_\+\+BB}~RCC\+\_\+\+CR\+\_\+\+HSION\+\_\+\+BB
\item 
\#define {\bfseries CR\+\_\+\+CSSON\+\_\+\+BB}~RCC\+\_\+\+CR\+\_\+\+CSSON\+\_\+\+BB
\item 
\#define {\bfseries CR\+\_\+\+PLLON\+\_\+\+BB}~RCC\+\_\+\+CR\+\_\+\+PLLON\+\_\+\+BB
\item 
\#define {\bfseries CR\+\_\+\+PLLI2\+SON\+\_\+\+BB}~RCC\+\_\+\+CR\+\_\+\+PLLI2\+SON\+\_\+\+BB
\item 
\#define {\bfseries CR\+\_\+\+MSION\+\_\+\+BB}~RCC\+\_\+\+CR\+\_\+\+MSION\+\_\+\+BB
\item 
\#define {\bfseries CSR\+\_\+\+LSION\+\_\+\+BB}~RCC\+\_\+\+CSR\+\_\+\+LSION\+\_\+\+BB
\item 
\#define {\bfseries CSR\+\_\+\+LSEON\+\_\+\+BB}~RCC\+\_\+\+CSR\+\_\+\+LSEON\+\_\+\+BB
\item 
\#define {\bfseries CSR\+\_\+\+LSEBYP\+\_\+\+BB}~RCC\+\_\+\+CSR\+\_\+\+LSEBYP\+\_\+\+BB
\item 
\#define {\bfseries CSR\+\_\+\+RTCEN\+\_\+\+BB}~RCC\+\_\+\+CSR\+\_\+\+RTCEN\+\_\+\+BB
\item 
\#define {\bfseries CSR\+\_\+\+RTCRST\+\_\+\+BB}~RCC\+\_\+\+CSR\+\_\+\+RTCRST\+\_\+\+BB
\item 
\#define {\bfseries CFGR\+\_\+\+I2\+SSRC\+\_\+\+BB}~RCC\+\_\+\+CFGR\+\_\+\+I2\+SSRC\+\_\+\+BB
\item 
\#define {\bfseries BDCR\+\_\+\+RTCEN\+\_\+\+BB}~RCC\+\_\+\+BDCR\+\_\+\+RTCEN\+\_\+\+BB
\item 
\#define {\bfseries BDCR\+\_\+\+BDRST\+\_\+\+BB}~RCC\+\_\+\+BDCR\+\_\+\+BDRST\+\_\+\+BB
\item 
\#define {\bfseries CR\+\_\+\+HSEON\+\_\+\+BB}~RCC\+\_\+\+CR\+\_\+\+HSEON\+\_\+\+BB
\item 
\#define {\bfseries CSR\+\_\+\+RMVF\+\_\+\+BB}~RCC\+\_\+\+CSR\+\_\+\+RMVF\+\_\+\+BB
\item 
\#define {\bfseries CR\+\_\+\+PLLSAION\+\_\+\+BB}~RCC\+\_\+\+CR\+\_\+\+PLLSAION\+\_\+\+BB
\item 
\#define {\bfseries DCKCFGR\+\_\+\+TIMPRE\+\_\+\+BB}~RCC\+\_\+\+DCKCFGR\+\_\+\+TIMPRE\+\_\+\+BB
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+ENABLE\+\_\+\+FREQ\+\_\+\+ERROR\+\_\+\+COUNTER}~\mbox{\hyperlink{group___r_c_c_ex___c_r_s___extended___features_ga59fe9365920d435138c487b85068cab0}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+FREQ\+\_\+\+ERROR\+\_\+\+COUNTER\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+DISABLE\+\_\+\+FREQ\+\_\+\+ERROR\+\_\+\+COUNTER}~\mbox{\hyperlink{group___r_c_c_ex___c_r_s___extended___features_ga92d96e3857c138d9a313f74de163e833}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+FREQ\+\_\+\+ERROR\+\_\+\+COUNTER\+\_\+\+DISABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+ENABLE\+\_\+\+AUTOMATIC\+\_\+\+CALIB}~\mbox{\hyperlink{group___r_c_c_ex___c_r_s___extended___features_gabed68fe74d544b1c602aa5a22a7af786}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+AUTOMATIC\+\_\+\+CALIB\+\_\+\+ENABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+DISABLE\+\_\+\+AUTOMATIC\+\_\+\+CALIB}~\mbox{\hyperlink{group___r_c_c_ex___c_r_s___extended___features_ga1a3b49219a5d79ba0688074b56d33122}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+AUTOMATIC\+\_\+\+CALIB\+\_\+\+DISABLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+CALCULATE\+\_\+\+RELOADVALUE}~\mbox{\hyperlink{group___r_c_c_ex___c_r_s___extended___features_ga5c48aa81c5416362a3cbb499754754a1}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+CRS\+\_\+\+RELOADVALUE\+\_\+\+CALCULATE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+IT\+\_\+\+SOURCE}~\mbox{\hyperlink{group___r_c_c___flags___interrupts___management_ga134af980b892f362c05ae21922cd828d}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+IT}}
\item 
\#define {\bfseries RCC\+\_\+\+CRS\+\_\+\+SYNCWARM}~RCC\+\_\+\+CRS\+\_\+\+SYNCWARN
\item 
\#define {\bfseries RCC\+\_\+\+CRS\+\_\+\+TRIMOV}~RCC\+\_\+\+CRS\+\_\+\+TRIMOVF
\item 
\#define {\bfseries RCC\+\_\+\+PERIPHCLK\+\_\+\+CK48}~RCC\+\_\+\+PERIPHCLK\+\_\+\+CLK48
\item 
\#define {\bfseries RCC\+\_\+\+CK48\+CLKSOURCE\+\_\+\+PLLQ}~RCC\+\_\+\+CLK48\+CLKSOURCE\+\_\+\+PLLQ
\item 
\#define {\bfseries RCC\+\_\+\+CK48\+CLKSOURCE\+\_\+\+PLLSAIP}~RCC\+\_\+\+CLK48\+CLKSOURCE\+\_\+\+PLLSAIP
\item 
\#define {\bfseries RCC\+\_\+\+CK48\+CLKSOURCE\+\_\+\+PLLI2\+SQ}~RCC\+\_\+\+CLK48\+CLKSOURCE\+\_\+\+PLLI2\+SQ
\item 
\#define {\bfseries IS\+\_\+\+RCC\+\_\+\+CK48\+CLKSOURCE}~IS\+\_\+\+RCC\+\_\+\+CLK48\+CLKSOURCE
\item 
\#define {\bfseries RCC\+\_\+\+SDIOCLKSOURCE\+\_\+\+CK48}~RCC\+\_\+\+SDIOCLKSOURCE\+\_\+\+CLK48
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+CLK\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+CLK\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+DISABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+FORCE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+FORCE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+RELEASE\+\_\+\+RESET}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+RELEASE\+\_\+\+RESET
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED}~\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+IS\+\_\+\+CLK\+\_\+\+SLEEP\+\_\+\+DISABLED
\item 
\#define {\bfseries Dfsdm\+Clock\+Selection}~Dfsdm1\+Clock\+Selection
\item 
\#define {\bfseries RCC\+\_\+\+PERIPHCLK\+\_\+\+DFSDM}~RCC\+\_\+\+PERIPHCLK\+\_\+\+DFSDM1
\item 
\#define {\bfseries RCC\+\_\+\+DFSDMCLKSOURCE\+\_\+\+PCLK}~RCC\+\_\+\+DFSDM1\+CLKSOURCE\+\_\+\+PCLK2
\item 
\#define {\bfseries RCC\+\_\+\+DFSDMCLKSOURCE\+\_\+\+SYSCLK}~RCC\+\_\+\+DFSDM1\+CLKSOURCE\+\_\+\+SYSCLK
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM\+\_\+\+CONFIG}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga79c4e732154d11fb10e6b5752ab31fc4}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+DFSDM1\+\_\+\+CONFIG}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+DFSDM\+\_\+\+SOURCE}~\mbox{\hyperlink{group___r_c_c_ex___exported___macros_ga5bd849cb75a56ae9a27a164e7d3c8575}{\+\_\+\+\_\+\+HAL\+\_\+\+RCC\+\_\+\+GET\+\_\+\+DFSDM1\+\_\+\+SOURCE}}
\item 
\#define {\bfseries RCC\+\_\+\+DFSDM1\+CLKSOURCE\+\_\+\+PCLK}~RCC\+\_\+\+DFSDM1\+CLKSOURCE\+\_\+\+PCLK2
\item 
\#define {\bfseries RCC\+\_\+\+SWPMI1\+CLKSOURCE\+\_\+\+PCLK}~RCC\+\_\+\+SWPMI1\+CLKSOURCE\+\_\+\+PCLK1
\item 
\#define {\bfseries RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+PCLK}~RCC\+\_\+\+LPTIM1\+CLKSOURCE\+\_\+\+PCLK1
\item 
\#define {\bfseries RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+PCLK}~RCC\+\_\+\+LPTIM2\+CLKSOURCE\+\_\+\+PCLK1
\item 
\#define {\bfseries RCC\+\_\+\+DFSDM1\+AUDIOCLKSOURCE\+\_\+\+I2\+SAPB1}~RCC\+\_\+\+DFSDM1\+AUDIOCLKSOURCE\+\_\+\+I2\+S1
\item 
\#define {\bfseries RCC\+\_\+\+DFSDM1\+AUDIOCLKSOURCE\+\_\+\+I2\+SAPB2}~RCC\+\_\+\+DFSDM1\+AUDIOCLKSOURCE\+\_\+\+I2\+S2
\item 
\#define {\bfseries RCC\+\_\+\+DFSDM2\+AUDIOCLKSOURCE\+\_\+\+I2\+SAPB1}~RCC\+\_\+\+DFSDM2\+AUDIOCLKSOURCE\+\_\+\+I2\+S1
\item 
\#define {\bfseries RCC\+\_\+\+DFSDM2\+AUDIOCLKSOURCE\+\_\+\+I2\+SAPB2}~RCC\+\_\+\+DFSDM2\+AUDIOCLKSOURCE\+\_\+\+I2\+S2
\item 
\#define {\bfseries RCC\+\_\+\+DFSDM1\+CLKSOURCE\+\_\+\+APB2}~RCC\+\_\+\+DFSDM1\+CLKSOURCE\+\_\+\+PCLK2
\item 
\#define {\bfseries RCC\+\_\+\+DFSDM2\+CLKSOURCE\+\_\+\+APB2}~RCC\+\_\+\+DFSDM2\+CLKSOURCE\+\_\+\+PCLK2
\item 
\#define {\bfseries RCC\+\_\+\+FMPI2\+C1\+CLKSOURCE\+\_\+\+APB}~RCC\+\_\+\+FMPI2\+C1\+CLKSOURCE\+\_\+\+PCLK1
\item 
\#define \mbox{\hyperlink{group___h_a_l___r_n_g___aliased___macros_gae0a40bc008a77b2f6f6bbe2c3d4bf978}{HAL\+\_\+\+RNG\+\_\+\+Ready\+Callback}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+CLEAR\+\_\+\+FLAG}~\+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+DISABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+ENABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT
\item 
\#define \mbox{\hyperlink{group___h_a_l___r_t_c___aliased___macros_ga70c16094f7c10e5991b608df36ce41f8}{\+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG}}(\+\_\+\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___h_a_l___r_t_c___aliased___macros_ga16764e0df245c740813dbeb302e67da5}{\+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___h_a_l___r_t_c___aliased___macros_ga9b18753e4b04bf550e36d81a6064ba36}{\+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___h_a_l___r_t_c___aliased___macros_ga7ff2ab63c65042a0a9ef683d345abf49}{\+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG}}(\+\_\+\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+\_\+)
\item 
\#define \mbox{\hyperlink{group___h_a_l___r_t_c___aliased___macros_ga757e6b82b6c280b6a924c0d8ac4bfef7}{\+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT}}(\+\_\+\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+\_\+)
\item 
\#define {\bfseries IS\+\_\+\+ALARM}~IS\+\_\+\+RTC\+\_\+\+ALARM
\item 
\#define {\bfseries IS\+\_\+\+ALARM\+\_\+\+MASK}~IS\+\_\+\+RTC\+\_\+\+ALARM\+\_\+\+MASK
\item 
\#define {\bfseries IS\+\_\+\+TAMPER}~IS\+\_\+\+RTC\+\_\+\+TAMPER
\item 
\#define {\bfseries IS\+\_\+\+TAMPER\+\_\+\+ERASE\+\_\+\+MODE}~IS\+\_\+\+RTC\+\_\+\+TAMPER\+\_\+\+ERASE\+\_\+\+MODE
\item 
\#define {\bfseries IS\+\_\+\+TAMPER\+\_\+\+FILTER}~IS\+\_\+\+RTC\+\_\+\+TAMPER\+\_\+\+FILTER
\item 
\#define {\bfseries IS\+\_\+\+TAMPER\+\_\+\+INTERRUPT}~IS\+\_\+\+RTC\+\_\+\+TAMPER\+\_\+\+INTERRUPT
\item 
\#define {\bfseries IS\+\_\+\+TAMPER\+\_\+\+MASKFLAG\+\_\+\+STATE}~IS\+\_\+\+RTC\+\_\+\+TAMPER\+\_\+\+MASKFLAG\+\_\+\+STATE
\item 
\#define {\bfseries IS\+\_\+\+TAMPER\+\_\+\+PRECHARGE\+\_\+\+DURATION}~IS\+\_\+\+RTC\+\_\+\+TAMPER\+\_\+\+PRECHARGE\+\_\+\+DURATION
\item 
\#define {\bfseries IS\+\_\+\+TAMPER\+\_\+\+PULLUP\+\_\+\+STATE}~IS\+\_\+\+RTC\+\_\+\+TAMPER\+\_\+\+PULLUP\+\_\+\+STATE
\item 
\#define {\bfseries IS\+\_\+\+TAMPER\+\_\+\+SAMPLING\+\_\+\+FREQ}~IS\+\_\+\+RTC\+\_\+\+TAMPER\+\_\+\+SAMPLING\+\_\+\+FREQ
\item 
\#define {\bfseries IS\+\_\+\+TAMPER\+\_\+\+TIMESTAMPONTAMPER\+\_\+\+DETECTION}~IS\+\_\+\+RTC\+\_\+\+TAMPER\+\_\+\+TIMESTAMPONTAMPER\+\_\+\+DETECTION
\item 
\#define {\bfseries IS\+\_\+\+TAMPER\+\_\+\+TRIGGER}~IS\+\_\+\+RTC\+\_\+\+TAMPER\+\_\+\+TRIGGER
\item 
\#define {\bfseries IS\+\_\+\+WAKEUP\+\_\+\+CLOCK}~IS\+\_\+\+RTC\+\_\+\+WAKEUP\+\_\+\+CLOCK
\item 
\#define {\bfseries IS\+\_\+\+WAKEUP\+\_\+\+COUNTER}~IS\+\_\+\+RTC\+\_\+\+WAKEUP\+\_\+\+COUNTER
\item 
\#define {\bfseries \+\_\+\+\_\+\+RTC\+\_\+\+WRITEPROTECTION\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+WRITEPROTECTION\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+RTC\+\_\+\+WRITEPROTECTION\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+RTC\+\_\+\+WRITEPROTECTION\+\_\+\+DISABLE
\item 
\#define {\bfseries SD\+\_\+\+OCR\+\_\+\+CID\+\_\+\+CSD\+\_\+\+OVERWRIETE}~SD\+\_\+\+OCR\+\_\+\+CID\+\_\+\+CSD\+\_\+\+OVERWRITE
\item 
\#define {\bfseries SD\+\_\+\+CMD\+\_\+\+SD\+\_\+\+APP\+\_\+\+STAUS}~SD\+\_\+\+CMD\+\_\+\+SD\+\_\+\+APP\+\_\+\+STATUS
\item 
\#define {\bfseries e\+MMC\+\_\+\+HIGH\+\_\+\+VOLTAGE\+\_\+\+RANGE}~EMMC\+\_\+\+HIGH\+\_\+\+VOLTAGE\+\_\+\+RANGE
\item 
\#define {\bfseries e\+MMC\+\_\+\+DUAL\+\_\+\+VOLTAGE\+\_\+\+RANGE}~EMMC\+\_\+\+DUAL\+\_\+\+VOLTAGE\+\_\+\+RANGE
\item 
\#define {\bfseries e\+MMC\+\_\+\+LOW\+\_\+\+VOLTAGE\+\_\+\+RANGE}~EMMC\+\_\+\+LOW\+\_\+\+VOLTAGE\+\_\+\+RANGE
\item 
\#define {\bfseries SDMMC\+\_\+\+NSpeed\+\_\+\+CLK\+\_\+\+DIV}~SDMMC\+\_\+\+NSPEED\+\_\+\+CLK\+\_\+\+DIV
\item 
\#define {\bfseries SDMMC\+\_\+\+HSpeed\+\_\+\+CLK\+\_\+\+DIV}~SDMMC\+\_\+\+HSPEED\+\_\+\+CLK\+\_\+\+DIV
\item 
\#define {\bfseries \+\_\+\+\_\+\+SMARTCARD\+\_\+\+ENABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+SMARTCARD\+\_\+\+ENABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+SMARTCARD\+\_\+\+DISABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+SMARTCARD\+\_\+\+DISABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+SMARTCARD\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+SMARTCARD\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SMARTCARD\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+SMARTCARD\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SMARTCARD\+\_\+\+DMA\+\_\+\+REQUEST\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+SMARTCARD\+\_\+\+DMA\+\_\+\+REQUEST\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SMARTCARD\+\_\+\+DMA\+\_\+\+REQUEST\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+SMARTCARD\+\_\+\+DMA\+\_\+\+REQUEST\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SMARTCARD\+\_\+\+GETCLOCKSOURCE}~SMARTCARD\+\_\+\+GETCLOCKSOURCE
\item 
\#define {\bfseries \+\_\+\+\_\+\+SMARTCARD\+\_\+\+GETCLOCKSOURCE}~SMARTCARD\+\_\+\+GETCLOCKSOURCE
\item 
\#define {\bfseries IS\+\_\+\+SMARTCARD\+\_\+\+ONEBIT\+\_\+\+SAMPLING}~IS\+\_\+\+SMARTCARD\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SMBUS\+\_\+\+RESET\+\_\+\+CR1}~SMBUS\+\_\+\+RESET\+\_\+\+CR1
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SMBUS\+\_\+\+RESET\+\_\+\+CR2}~SMBUS\+\_\+\+RESET\+\_\+\+CR2
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SMBUS\+\_\+\+GENERATE\+\_\+\+START}~SMBUS\+\_\+\+GENERATE\+\_\+\+START
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SMBUS\+\_\+\+GET\+\_\+\+ADDR\+\_\+\+MATCH}~SMBUS\+\_\+\+GET\+\_\+\+ADDR\+\_\+\+MATCH
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SMBUS\+\_\+\+GET\+\_\+\+DIR}~SMBUS\+\_\+\+GET\+\_\+\+DIR
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SMBUS\+\_\+\+GET\+\_\+\+STOP\+\_\+\+MODE}~SMBUS\+\_\+\+GET\+\_\+\+STOP\+\_\+\+MODE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SMBUS\+\_\+\+GET\+\_\+\+PEC\+\_\+\+MODE}~SMBUS\+\_\+\+GET\+\_\+\+PEC\+\_\+\+MODE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SMBUS\+\_\+\+GET\+\_\+\+ALERT\+\_\+\+ENABLED}~SMBUS\+\_\+\+GET\+\_\+\+ALERT\+\_\+\+ENABLED
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+1\+LINE\+\_\+\+TX}~\mbox{\hyperlink{group___s_p_i___private___macros_gae3b2eb5e818e58b66474d42dedac5523}{SPI\+\_\+1\+LINE\+\_\+\+TX}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+1\+LINE\+\_\+\+RX}~\mbox{\hyperlink{group___s_p_i___private___macros_gaa8d58cef91c1874d5a4dde4014cf6269}{SPI\+\_\+1\+LINE\+\_\+\+RX}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+RESET\+\_\+\+CRC}~SPI\+\_\+\+RESET\+\_\+\+CRC
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UART\+\_\+\+GETCLOCKSOURCE}~\mbox{\hyperlink{group___u_a_r_t_ex___private___macros_ga2d8ffd4cb12754846ace609dff92e8df}{UART\+\_\+\+GETCLOCKSOURCE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+UART\+\_\+\+MASK\+\_\+\+COMPUTATION}~\mbox{\hyperlink{group___u_a_r_t_ex___private___macros_gad9330184a8bd9399a36bcc93215a50d1}{UART\+\_\+\+MASK\+\_\+\+COMPUTATION}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART\+\_\+\+GETCLOCKSOURCE}~\mbox{\hyperlink{group___u_a_r_t_ex___private___macros_ga2d8ffd4cb12754846ace609dff92e8df}{UART\+\_\+\+GETCLOCKSOURCE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+UART\+\_\+\+MASK\+\_\+\+COMPUTATION}~\mbox{\hyperlink{group___u_a_r_t_ex___private___macros_gad9330184a8bd9399a36bcc93215a50d1}{UART\+\_\+\+MASK\+\_\+\+COMPUTATION}}
\item 
\#define {\bfseries IS\+\_\+\+UART\+\_\+\+WAKEUPMETHODE}~\mbox{\hyperlink{group___u_a_r_t___private___macros_ga144aecf3ad6ca3ce6653ae113c9a6141}{IS\+\_\+\+UART\+\_\+\+WAKEUPMETHOD}}
\item 
\#define {\bfseries IS\+\_\+\+UART\+\_\+\+ONEBIT\+\_\+\+SAMPLE}~\mbox{\hyperlink{group___u_a_r_t___private___macros_ga6452a4420dac4abd4f0ea0e1677f37a9}{IS\+\_\+\+UART\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE}}
\item 
\#define {\bfseries IS\+\_\+\+UART\+\_\+\+ONEBIT\+\_\+\+SAMPLING}~\mbox{\hyperlink{group___u_a_r_t___private___macros_ga6452a4420dac4abd4f0ea0e1677f37a9}{IS\+\_\+\+UART\+\_\+\+ONE\+\_\+\+BIT\+\_\+\+SAMPLE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART\+\_\+\+ENABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+USART\+\_\+\+ENABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART\+\_\+\+DISABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+USART\+\_\+\+DISABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART\+\_\+\+ENABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+USART\+\_\+\+ENABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART\+\_\+\+DISABLE}~\+\_\+\+\_\+\+HAL\+\_\+\+USART\+\_\+\+DISABLE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USART\+\_\+\+GETCLOCKSOURCE}~USART\+\_\+\+GETCLOCKSOURCE
\item 
\#define {\bfseries \+\_\+\+\_\+\+USART\+\_\+\+GETCLOCKSOURCE}~USART\+\_\+\+GETCLOCKSOURCE
\item 
\#define {\bfseries USB\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+WAKEUP}~USB\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+LINE
\item 
\#define {\bfseries USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+TRIGGER\+\_\+\+RISING\+\_\+\+EDGE}~USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+RISING\+\_\+\+EDGE
\item 
\#define {\bfseries USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+TRIGGER\+\_\+\+FALLING\+\_\+\+EDGE}~USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+TRIGGER\+\_\+\+BOTH\+\_\+\+EDGE}~USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+WAKEUP}~USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+LINE
\item 
\#define {\bfseries USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+TRIGGER\+\_\+\+RISING\+\_\+\+EDGE}~USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+RISING\+\_\+\+EDGE
\item 
\#define {\bfseries USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+TRIGGER\+\_\+\+FALLING\+\_\+\+EDGE}~USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+TRIGGER\+\_\+\+BOTH\+\_\+\+EDGE}~USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+LINE\+\_\+\+WAKEUP}~USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+LINE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+RISING\+\_\+\+EDGE\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+FALLING\+\_\+\+EDGE\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+FALLINGRISING\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+RISING\+\_\+\+EGDE\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+FALLING\+\_\+\+EGDE\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+FALLINGRISING\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+FS\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+FS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+RISING\+\_\+\+EGDE\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+FALLING\+\_\+\+EGDE\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+FALLINGRISING\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+FALLING\+\_\+\+EDGE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+HS\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT}~\+\_\+\+\_\+\+HAL\+\_\+\+USB\+\_\+\+OTG\+\_\+\+HS\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+GENERATE\+\_\+\+SWIT
\item 
\#define {\bfseries HAL\+\_\+\+PCD\+\_\+\+Active\+Remote\+Wakeup}~HAL\+\_\+\+PCD\+\_\+\+Activate\+Remote\+Wakeup
\item 
\#define {\bfseries HAL\+\_\+\+PCD\+\_\+\+De\+Active\+Remote\+Wakeup}~HAL\+\_\+\+PCD\+\_\+\+De\+Activate\+Remote\+Wakeup
\item 
\#define {\bfseries HAL\+\_\+\+PCD\+\_\+\+Set\+Tx\+Fi\+Fo}~HAL\+\_\+\+PCDEx\+\_\+\+Set\+Tx\+Fi\+Fo
\item 
\#define {\bfseries HAL\+\_\+\+PCD\+\_\+\+Set\+Rx\+Fi\+Fo}~HAL\+\_\+\+PCDEx\+\_\+\+Set\+Rx\+Fi\+Fo
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Set\+ICPrescaler\+Value}~TIM\+\_\+\+SET\+\_\+\+ICPRESCALERVALUE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Reset\+ICPrescaler\+Value}~TIM\+\_\+\+RESET\+\_\+\+ICPRESCALERVALUE
\item 
\#define {\bfseries TIM\+\_\+\+GET\+\_\+\+ITSTATUS}~\mbox{\hyperlink{group___t_i_m___exported___macros_ga644babf93470a6eee6bce8906c4da5c5}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+GET\+\_\+\+IT\+\_\+\+SOURCE}}
\item 
\#define {\bfseries TIM\+\_\+\+GET\+\_\+\+CLEAR\+\_\+\+IT}~\mbox{\hyperlink{group___t_i_m___exported___macros_gaea68155ce77e591e0c2582def061d6f0}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+CLEAR\+\_\+\+IT}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+GET\+\_\+\+ITSTATUS}~\mbox{\hyperlink{group___t_i_m___exported___macros_ga644babf93470a6eee6bce8906c4da5c5}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+GET\+\_\+\+IT\+\_\+\+SOURCE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+DIRECTION\+\_\+\+STATUS}~\mbox{\hyperlink{group___t_i_m___exported___macros_gac73f5e7669d92971830481e7298e98ba}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+IS\+\_\+\+TIM\+\_\+\+COUNTING\+\_\+\+DOWN}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+PRESCALER}~\mbox{\hyperlink{group___t_i_m___exported___macros_gafdc5a06eab07e0c24e729fd492bdb27c}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+SET\+\_\+\+PRESCALER}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Set\+Counter}~\mbox{\hyperlink{group___t_i_m___exported___macros_ga9746ac75e4cd25cec1a9ebac8cb82b97}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+SET\+\_\+\+COUNTER}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Get\+Counter}~\mbox{\hyperlink{group___t_i_m___exported___macros_gaf1af08014b9d06efbbb091d58d47c8ba}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+GET\+\_\+\+COUNTER}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Set\+Autoreload}~\mbox{\hyperlink{group___t_i_m___exported___macros_ga1e6300cab1e34ecaaf490dc7d4812d69}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+SET\+\_\+\+AUTORELOAD}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Get\+Autoreload}~\mbox{\hyperlink{group___t_i_m___exported___macros_gaa7a5c7645695bad15bacd402513a028a}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+GET\+\_\+\+AUTORELOAD}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Set\+Clock\+Division}~\mbox{\hyperlink{group___t_i_m___exported___macros_ga8aa84d77c670890408092630f9b2bdc4}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+SET\+\_\+\+CLOCKDIVISION}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Get\+Clock\+Division}~\mbox{\hyperlink{group___t_i_m___exported___macros_gae6bc91bb5940bce52828c690f24001b8}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+GET\+\_\+\+CLOCKDIVISION}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Set\+ICPrescaler}~\mbox{\hyperlink{group___t_i_m___exported___macros_gaeb106399b95ef02cec502f58276a0e92}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+SET\+\_\+\+ICPRESCALER}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Get\+ICPrescaler}~\mbox{\hyperlink{group___t_i_m___exported___macros_gabfeec6b3c67a5747c7dbd20aff61d8e2}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+GET\+\_\+\+ICPRESCALER}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Set\+Compare}~\mbox{\hyperlink{group___t_i_m___exported___macros_ga300d0c9624c3b072d3afeb7cef639b66}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+SET\+\_\+\+COMPARE}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+Get\+Compare}~\mbox{\hyperlink{group___t_i_m___exported___macros_gaa40722f56910966e1da5241b610eed84}{\+\_\+\+\_\+\+HAL\+\_\+\+TIM\+\_\+\+GET\+\_\+\+COMPARE}}
\item 
\#define {\bfseries TIM\+\_\+\+BREAKINPUTSOURCE\+\_\+\+DFSDM}~TIM\+\_\+\+BREAKINPUTSOURCE\+\_\+\+DFSDM1
\item 
\#define {\bfseries TIM\+\_\+\+OCMODE\+\_\+\+ASSYMETRIC\+\_\+\+PWM1}~\mbox{\hyperlink{group___t_i_m___output___compare__and___p_w_m__modes_gac1c1f898f74a95c15bd1cee91c636a82}{TIM\+\_\+\+OCMODE\+\_\+\+ASYMMETRIC\+\_\+\+PWM1}}
\item 
\#define {\bfseries TIM\+\_\+\+OCMODE\+\_\+\+ASSYMETRIC\+\_\+\+PWM2}~\mbox{\hyperlink{group___t_i_m___output___compare__and___p_w_m__modes_ga475c44a172e981d0d96e51dd811d2705}{TIM\+\_\+\+OCMODE\+\_\+\+ASYMMETRIC\+\_\+\+PWM2}}
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT}~\+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+DISABLE\+\_\+\+IT
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG}~\+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+GET\+\_\+\+FLAG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG}~\+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+CLEAR\+\_\+\+FLAG
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+RISING\+\_\+\+EGDE\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+RISING\+\_\+\+EDGE\+\_\+\+TRIGGER
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+FALLING\+\_\+\+EGDE\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLING\+\_\+\+EDGE\+\_\+\+TRIGGER
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+EXTI\+\_\+\+SET\+\_\+\+FALLINGRISING\+\_\+\+TRIGGER}~\+\_\+\+\_\+\+HAL\+\_\+\+ETH\+\_\+\+WAKEUP\+\_\+\+EXTI\+\_\+\+ENABLE\+\_\+\+FALLINGRISING\+\_\+\+TRIGGER
\item 
\#define {\bfseries ETH\+\_\+\+PROMISCIOUSMODE\+\_\+\+ENABLE}~ETH\+\_\+\+PROMISCUOUS\+\_\+\+MODE\+\_\+\+ENABLE
\item 
\#define {\bfseries ETH\+\_\+\+PROMISCIOUSMODE\+\_\+\+DISABLE}~ETH\+\_\+\+PROMISCUOUS\+\_\+\+MODE\+\_\+\+DISABLE
\item 
\#define {\bfseries IS\+\_\+\+ETH\+\_\+\+PROMISCIOUS\+\_\+\+MODE}~IS\+\_\+\+ETH\+\_\+\+PROMISCUOUS\+\_\+\+MODE
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+LTDC\+\_\+\+LAYER}~LTDC\+\_\+\+LAYER
\item 
\#define {\bfseries \+\_\+\+\_\+\+HAL\+\_\+\+LTDC\+\_\+\+RELOAD\+\_\+\+CONFIG}~\+\_\+\+\_\+\+HAL\+\_\+\+LTDC\+\_\+\+RELOAD\+\_\+\+IMMEDIATE\+\_\+\+CONFIG
\item 
\#define {\bfseries SAI\+\_\+\+OUTPUTDRIVE\+\_\+\+DISABLED}~SAI\+\_\+\+OUTPUTDRIVE\+\_\+\+DISABLE
\item 
\#define {\bfseries SAI\+\_\+\+OUTPUTDRIVE\+\_\+\+ENABLED}~SAI\+\_\+\+OUTPUTDRIVE\+\_\+\+ENABLE
\item 
\#define {\bfseries SAI\+\_\+\+MASTERDIVIDER\+\_\+\+ENABLED}~SAI\+\_\+\+MASTERDIVIDER\+\_\+\+ENABLE
\item 
\#define {\bfseries SAI\+\_\+\+MASTERDIVIDER\+\_\+\+DISABLED}~SAI\+\_\+\+MASTERDIVIDER\+\_\+\+DISABLE
\item 
\#define {\bfseries SAI\+\_\+\+STREOMODE}~SAI\+\_\+\+STEREOMODE
\item 
\#define {\bfseries SAI\+\_\+\+FIFOStatus\+\_\+\+Empty}~SAI\+\_\+\+FIFOSTATUS\+\_\+\+EMPTY
\item 
\#define {\bfseries SAI\+\_\+\+FIFOStatus\+\_\+\+Less1\+Quarter\+Full}~SAI\+\_\+\+FIFOSTATUS\+\_\+\+LESS1\+QUARTERFULL
\item 
\#define {\bfseries SAI\+\_\+\+FIFOStatus\+\_\+1\+Quarter\+Full}~SAI\+\_\+\+FIFOSTATUS\+\_\+1\+QUARTERFULL
\item 
\#define {\bfseries SAI\+\_\+\+FIFOStatus\+\_\+\+Half\+Full}~SAI\+\_\+\+FIFOSTATUS\+\_\+\+HALFFULL
\item 
\#define {\bfseries SAI\+\_\+\+FIFOStatus\+\_\+3\+Quarters\+Full}~SAI\+\_\+\+FIFOSTATUS\+\_\+3\+QUARTERFULL
\item 
\#define {\bfseries SAI\+\_\+\+FIFOStatus\+\_\+\+Full}~SAI\+\_\+\+FIFOSTATUS\+\_\+\+FULL
\item 
\#define {\bfseries IS\+\_\+\+SAI\+\_\+\+BLOCK\+\_\+\+MONO\+\_\+\+STREO\+\_\+\+MODE}~IS\+\_\+\+SAI\+\_\+\+BLOCK\+\_\+\+MONO\+\_\+\+STEREO\+\_\+\+MODE
\item 
\#define {\bfseries SAI\+\_\+\+SYNCHRONOUS\+\_\+\+EXT}~SAI\+\_\+\+SYNCHRONOUS\+\_\+\+EXT\+\_\+\+SAI1
\item 
\#define {\bfseries SAI\+\_\+\+SYNCEXT\+\_\+\+IN\+\_\+\+ENABLE}~SAI\+\_\+\+SYNCEXT\+\_\+\+OUTBLOCKA\+\_\+\+ENABLE
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
This file contains aliases definition for the STM32\+Cube HAL constants macros and functions maintained for legacy purpose. 

\begin{DoxyAuthor}{Author}
MCD Application Team 
\end{DoxyAuthor}
\begin{DoxyAttention}{Attention}

\end{DoxyAttention}
Copyright (c) 2021 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-\/\+IS. 